/******************** (C) COPYRIGHT 2021 CHIPAT ********************
* File Name          : TC32L010.h
* Author             : 24538
* Version            : V1.0.0
* Date               : 10/05/2021
* Description        : CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
*                      This file contains all the peripheral register's definitions, bits
*                      definitions and memory mapping for tc32l010 devices.
*
*                      This file contains:
*                      - Data structures and the address mapping for all peripherals
*                      - Peripheral's registers declarations and bits definition
*                      - Macros to access peripheral's registers hardware
*****************************************************************************/


/** @addtogroup CMSIS
  * @{
  */

/** @addtogroup tc32l010
  * @{
  */

#ifndef __XS32L010_H
#define __XS32L010_H

#ifdef __cplusplus
extern "C" {
#endif


/* ########################## Module Selection ############################## */


#define XTAL_32768HZ                  32768U
#define XTAL_1000000HZ                1000000U
#define XTAL_2000000HZ                2000000U
#define XTAL_4000000HZ                4000000U
#define XTAL_8000000HZ                8000000U
#define XTAL_12000000HZ               12000000U
#define XTAL_24000000HZ               24000000U

#if !defined  (LSE_VALUE)
#define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* MSI_VALUE */

#if !defined  (HSE_VALUE)
#define HSE_VALUE    ((uint32_t)24000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

#if !defined  (LSI_VALUE)
#define LSI_VALUE    ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */

#if !defined  (HSI_VALUE)
  #define HSI_VALUE_H    ((uint32_t)24000000U) /*!< Value of the Internal oscillator in Hz*/ 
  #define HSI_VALUE_L    ((uint32_t)4000000U)  /*!< Value of the Internal oscillator in Hz*/ 
#endif /* HSI_VALUE */



/* ########################### System Configuration ######################### */
/**
  * @brief This is the HAL system configuration section
  */
#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */
#define  USE_RTOS                     0U
#define  PREFETCH_ENABLE              0U
#define  PREREAD_ENABLE               0U
#define  BUFFER_CACHE_DISABLE         0U


/* ########################## Assert Selection ############################## */
/**
  * @brief Uncomment the line below to expanse the "assert_param" macro in the
  *        HAL drivers code
  */
/* #define USE_FULL_ASSERT    1U */

/* Includes ------------------------------------------------------------------*/
/**
  * @brief Include module's header file
  */
#if !defined  (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
#endif /* HSE_STARTUP_TIMEOUT */



/* Exported macro ------------------------------------------------------------*/
#ifdef  USE_FULL_ASSERT
/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param  expr: If expr is false, it calls assert_failed function
  *         which reports the name of the source file and the source
  *         line number of the call that failed.
  *         If expr is true, it returns no value.
  * @retval None
  */
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

/**
  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
#define __MPU_PRESENT             1 /*!< tc32l010  provides an MPU                    */
#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
#define __NVIC_PRIO_BITS          2 /*!< tc32l010 uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */

/**
  * @}
  */

/*!< Interrupt Number Definition */
typedef enum
{
    /******  Cortex-M0+ Processor Exceptions Numbers ******************************************************/
    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                  */
    HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                         */
    SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                           */
    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                           */
    SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                       */

    /******  TC32L010 specific Interrupt Numbers *********************************************************/
    GPA_IRQn                    = 0,      /*!< GPIOA Interrupt                                           */
    GPB_IRQn                    = 1,      /*!< GPIOB Interrupt                                           */
    GPC_IRQn                    = 2,      /*!< GPIOC Interrupt                                           */
    GPD_IRQn                    = 3,      /*!< GPIOD Interrupt                                           */
    FLASH_IRQn                  = 4,      /*!< FLASH Interrupt                                           */
    DMACH1_IRQn                 = 5,      /*!< DMA_CH1 Interrupt                                         */
    USART0_IRQn                 = 6,      /*!< USART0 Interrupt                                          */
    USART1_IRQn                 = 7,      /*!< USART1 Interrupt                                          */
    LPUART_IRQn                 = 8,      /*!< LPUSART Interrupt                                         */
    DMACH2_IRQn                 = 9,      /*!< DMA_CH2 Interrupt                                         */
    SPI_IRQn                    = 10,     /*!< SPI Interrupt                                             */
    I2C0_IRQn                   = 12,     /*!< I2C Interrupt                                             */
    TIM4_IRQn                   = 14,     /*!< TIM4 Interrupt                                            */
    TIM5_IRQn                   = 15,     /*!< TIM5 Interrupt                                            */
    LPTIM_IRQn                  = 16,     /*!< LPTIM Interrupt                                           */
    TIM1_BRK_UP_TRG_COM_IRQn    = 18,     /*!< TIM1_BRK_UP_TRG_COM Interrupt                             */
    TIM2_IRQn                   = 19,     /*!< TIM2 Interrupt                                            */
    TIM1_CC_IRQn                = 20,     /*!< TIM1 CC Interrupt                                         */
    PCA_IRQn                    = 21,     /*!< PCA(TIM3) Interrupt                                       */
    WWDG_IRQn                   = 22,     /*!< WWDG Interrupt                                            */
    ADC_IRQn                    = 24,     /*!< ADC Interrupt                                             */
    LVD_IRQn                    = 25,     /*!< LVD Interrupt                                             */ 
    RTC_WKUP_IRQn               = 28,     /*!< RTC_WKUP Interrupt                                        */
    RTC_ALRAM_IRQn              = 30,     /*!< RTC_ALRAM Interrupt                                       */
    RCC_IRQn                    = 31,     /*!< RCC Interrupt                                             */
} IRQn_Type;

/**
  * @}
  */

/** @addtogroup Configuration_section_for_CMSIS
  * @{
  */

/**
  * @}
  */
#include "tc32l010.h"
#include "core_cm0plus.h"
#include "system_tc32l010.h"
#include <stdint.h>


/** @addtogroup Exported_types
  * @{
  */

typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;


/** @addtogroup Peripheral_registers_structures
  * @{
  */

/**
  * @brief Analog to Digital Converter
  */

typedef struct
{
    __IO uint32_t CR0;             /*offset=0x00*/
    __IO uint32_t CR1;             /*offset=0x04*/
    __IO uint32_t CR2;             /*offset=0x08*/
    __IO uint32_t RESULT0;         /*offset=0x0C*/
    __IO uint32_t RESULT1;         /*offset=0x10*/
    __IO uint32_t RESULT2;         /*offset=0x14*/
    __IO uint32_t RESULT3;         /*offset=0x18*/
    __IO uint32_t RESULT4;         /*offset=0x0C*/
    __IO uint32_t RESULT5;         /*offset=0x20*/
    __IO uint32_t RESULT6;         /*offset=0x24*/
    __IO uint32_t RESULT7;         /*offset=0x28*/
    __IO uint32_t RESULT;          /*offset=0x2C*/
    __IO uint32_t RESULT_ACC;      /*offset=0x30*/
    __IO uint32_t THRESHOLD;       /*offset=0x34*/
    __IO uint32_t INTEN;           /*offset=0x38*/
    __IO uint32_t RAWINTSR;        /*offset=0x3C*/
    __IO uint32_t MSKINTSR;        /*offset=0x40*/
    __IO uint32_t TIME;            /*offset=0x44*/
} ADC_TypeDef;


/**
  * @brief CRC calculation unit
  */

typedef struct
{
    uint32_t RESULT    :16;
    uint32_t FLAG      :1;
} CRC_Resultfield;

typedef struct
{
    uint32_t RESERVED0;
    CRC_Resultfield  RESULT;          /*!< CRC Data register,                           Address offset: 0x04 */
    uint32_t RESERVED1[30];
    __IO uint32_t  DATA;              /*!< CRC Independent data register,               Address offset: 0x80 */
} CRC_TypeDef;


/**
  * @brief Debug MCU
  */

typedef struct
{
    __IO uint32_t IDCODE;          /*!< MCU device ID code,                          Address offset: 0x00 */
    __IO uint32_t CR;              /*!< Debug MCU configuration register,            Address offset: 0x04 */
    __IO uint32_t APB1FZ;          /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
    __IO uint32_t APB2FZ;          /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
} DBGMCU_TypeDef;


/**
  * @brief DMA Controller
  */
typedef struct
{
    __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
    __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
    __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
    __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
} DMA_Channel_TypeDef;

typedef struct
{
    __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
    __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
    uint32_t      RESERVED0[40];/*!< Reserved as declared by channel typedef                         0x08 - 0xA4*/
    __IO uint32_t CSELR;        /*!< Remap control register,                                   Address offset: 0xA8 */
} DMA_TypeDef;


/**
  * @brief FLASH Registers
  */

typedef struct
{
    __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x00 */
    __IO uint32_t IFR;      /*!< Flash Interrupt Flag register,   Address offset: 0x04 */
    __IO uint32_t WRPR;     /*!< FLASH write protect register,    Address offset: 0x08 */
    __IO uint32_t BYPASS;   /*!< FLASH access control register,   Address offset: 0x0C */
    __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x10 */
    uint32_t RESERVED0;     /*!< Reserved,                        Address offset: 0x14 */
    __IO uint32_t DPDKEY;   /*!< DPDKEY unlock register,          Address offset: 0x18 */
    __IO uint32_t TIMMING;  /*!< TIMMING register,                Address offset: 0x1C */
} FLASH_TypeDef;


/**
  * @brief General Purpose I/O
  */

typedef struct {                                 /*!< (@ 0x40021000) GPIO Structure                                             */
    __IO uint32_t  DIRCR;                        /*!< (@ 0x00000000) Input Output model Register                                */
    __IO uint32_t  ODR;                          /*!< (@ 0x00000004) Output Data Register                                       */
    __IO uint32_t  IDR;                          /*!< (@ 0x00000008) Input Data Register                                        */
    __IO uint32_t  INTEN;                        /*!< (@ 0x0000000C) Inerrupt Enable Register                                   */
    __IO uint32_t  RAWINTSR;                     /*!< (@ 0x00000010) Interrupt Raw Status register                              */
    __IO uint32_t  MSKINTSR;                     /*!< (@ 0x00000014) Interrupt Status Register                                  */
    __IO uint32_t  INTCLR;                       /*!< (@ 0x00000018) Interrupt Clear Register                                   */
    __IO uint32_t  INTTYPECR;                    /*!< (@ 0x0000001C) Interrupt Style Register                                   */
    __IO uint32_t  INTPOLCR;                     /*!< (@ 0x00000020) Interrupt Sytle Value Register                             */
    __IO uint32_t  INTANY;                       /*!< (@ 0x00000024) Edge Trigger Interrupt Register                            */
    __IO uint32_t  ODSET;                        /*!< (@ 0x00000028) Output Setting Register                                    */
    __IO uint32_t  ODCLR;                        /*!< (@ 0x0000002C) Output Clear Register                                      */
    __IO uint32_t  DBR;                          /*!< (@ 0x00000030) Input Debounce and synchronous Enable Register             */
    __IO uint32_t  PUPDR;                        /*!< (@ 0x00000034) PullUp and PullDown Register                               */
    __IO uint32_t  DRVCR;                        /*!< (@ 0x00000038) Driver Strength Config                                     */
    __IO uint32_t  AFR;                          /*!< (@ 0x0000003C) Multiplex Function Register                                */
    __IO uint32_t  IS;                           /*!< (@ 0x00000040) Input mode control Register                                */
} GPIO_TypeDef;


/**
  * @brief Inter-integrated Circuit Interface
  */

typedef struct
{
    __IO uint32_t CON;               /*!< I2C control register >*/
    __IO uint32_t TAR;               /*!< I2C target address register >*/
    __IO uint32_t SAR;               /*!< I2C slave address register >*/
    __IO uint32_t DATA_CMD;          /*!< I2C data\command register >*/
    __IO uint32_t SCL_CNT;           /*!< I2C speed bit register >*/
    __IO uint32_t INTR_STAT;         /*!< I2C interrupt state register >*/
    __IO uint32_t INTR_MASK;         /*!< I2C interrupt mask register >*/
    __IO uint32_t INTR_CLR;          /*!< I2C clear interrupt state register >*/
    __IO uint32_t STATUS;            /*!< I2C status register >*/
    __IO uint32_t SDA_SETUP;         /*!< I2C SDA setup register >*/
    __IO uint32_t TX_ABRT_SOURCE;    /*!< I2C tx abrt register >*/
    __IO uint32_t FS_SPKLEN;         /*!< I2C fs spklen register >*/ 
         uint32_t RESERVED0;
    __IO uint32_t ENABLE;            /*!< I2C enable register >*/
    __IO uint32_t INTR_RAWSTAT;      /*!< I2C interrupt raw state register >*/
         uint32_t RESERVED1;
    __IO uint32_t DMA_CR;            /*!< I2C DMA control register >*/
    __IO uint32_t DMA_TDLR;          /*!< I2C DMA transmit data level register >*/
    __IO uint32_t DMA_RDLR;          /*!< I2C DMA receive data level register >*/
} I2C_TypeDef;


/**
  * @brief Independent WATCHDOG
  */
typedef struct
{
    __IO uint32_t KR;         /*!< IWDG Key register,       Address offset: 0x00 */
    __IO uint32_t PR;         /*!< IWDG Prescaler register, Address offset: 0x04 */
    __IO uint32_t RLR;        /*!< IWDG Reload register,    Address offset: 0x08 */
    __IO uint32_t SR;         /*!< IWDG Status register,    Address offset: 0x0C */
    __IO uint32_t WINR;       /*!< IWDG Window register,    Address offset: 0x10 */
} IWDG_TypeDef;


/**
  * @brief LPTIMER
  */
typedef struct
{
    __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
    __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
    __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
    __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
    __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
    __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
    __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
    __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
} LPTIM_TypeDef;


/**
  * @brief LPUART
  */
typedef struct
{
    __IO uint32_t SR;          /*!< LPUART Status register,                             Address offset: 0x00 */
    __IO uint32_t DR;          /*!< LPUART data register,                               Address offset: 0x04 */
    __IO uint32_t BRR;         /*!< LPUART Baud rate register,                          Address offset: 0x08 */
    __IO uint32_t CR1;         /*!< LPUART Control1 register,                           Address offset: 0x0C */
    __IO uint32_t CR2;         /*!< LPUART Control2 register,                           Address offset: 0x10 */
    __IO uint32_t CR3;         /*!< LPUART Control3 register,                           Address offset: 0x14 */
} LPUART_TypeDef;


/**
  * @brief Option Bytes Registers
  */
typedef struct
{
    __IO uint8_t  RDP;             /*!< Read protection register,               Address offset: 0x00 */
    __IO uint8_t  USER;
         uint16_t RESERVED0;
    __IO uint32_t DATA;            /*!< data register,                          Address offset: 0x04 */
    __IO uint32_t WRP;             /*!< write protection Bytes 0, 1, 2, 3       Address offset: 0x08 */
         uint32_t RESERVED1;
    __IO uint8_t  SWD;             /*!< control register (isp)                  Address offset: 0x10 */
    __IO uint8_t  BOOT;            /*!< control register (swd)                  Address offset: 0x10 */
         uint16_t RESERVED2;
    __IO uint8_t  FLASHSIZE;
} OB_TypeDef;


/**
  * @brief PCA (PCA)
  */

typedef struct {                                 /*!< (@ 0x40001400) PCA Structure                                              */
    __IO uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */
    __IO uint32_t  MOD;                          /*!< (@ 0x00000004) Mode Register                                              */
    __IO uint32_t  CNT;                          /*!< (@ 0x00000008) PCA Count Register                                         */
         uint32_t  RESERVED0;                    
    __IO uint32_t  CCAPM0;                       /*!< (@ 0x00000010) PCA Captuer/Compare Model 0 Mode Register                  */
    __IO uint32_t  CCAPM1;                       /*!< (@ 0x00000014) PCA Captuer/Compare Model 0 Mode Register                  */
    __IO uint32_t  CCAPM2;                       /*!< (@ 0x00000018) PCA Captuer/Compare Model 0 Mode Register                  */
    __IO uint32_t  CCAPM3;                       /*!< (@ 0x0000001C) PCA Captuer/Compare Model 0 Mode Register                  */
    __IO uint32_t  CCAPM4;                       /*!< (@ 0x00000020) PCA Captuer/Compare Model 0 Mode Register                  */
         uint32_t  RESERVED1[3];
    __IO uint32_t  CCAP0L;                       /*!< (@ 0x00000030) PCA Capture/Compare Model0 Low 8 bits Register             */
    __IO uint32_t  CCAP0H;                       /*!< (@ 0x00000034) PCA Capture/Compare Model0 High 8 bits Register            */
    __IO uint32_t  CCAP1L;                       /*!< (@ 0x00000038) PCA Capture/Compare Model 1 Low 8 bits Register            */
    __IO uint32_t  CCAP1H;                       /*!< (@ 0x0000003C) PCA Capture/Compare Model 1 High 8 bits Register           */
    __IO uint32_t  CCAP2L;                       /*!< (@ 0x00000040) PCA Capture/Compare Model 2 Low 8 bits Register            */
    __IO uint32_t  CCAP2H;                       /*!< (@ 0x00000044) PCA Capture/Compare Model 2 High 8 bits Register           */
    __IO uint32_t  CCAP3L;                       /*!< (@ 0x00000048) PCA Capture/Compare Model 3 Low 8 bits Register            */
    __IO uint32_t  CCAP3H;                       /*!< (@ 0x0000004C) PCA Capture/Compare Model 3 High 8 bits Register           */
    __IO uint32_t  CCAP4L;                       /*!< (@ 0x00000050) PCA Capture/Compare Model 4 Low 8 bits Register            */
    __IO uint32_t  CCAP4H;                       /*!< (@ 0x00000054) PCA Capture/Compare Model 4 High 8 bits Register           */
    __IO uint32_t  CCAPO;                        /*!< (@ 0x00000058) PCA EndPoint Output Control Register                       */
    __IO uint32_t  POCR;                         /*!< (@ 0x0000005C) PCA EndPoint Output Control Register                       */
    __IO uint32_t  CCAP0;                        /*!< (@ 0x00000060) PCA Capture/Compare Model0 16 bits Register                */
    __IO uint32_t  CCAP1;                        /*!< (@ 0x00000064) PCA Capture/Compare Model 1 16 bits Register               */
    __IO uint32_t  CCAP2;                        /*!< (@ 0x00000068) PCA Capture/Compare Model 2 16 bits Register               */
    __IO uint32_t  CCAP3;                        /*!< (@ 0x0000006C) PCA Capture/Compare Model 3 16 bits Register               */
    __IO uint32_t  CCAP4;                        /*!< (@ 0x00000070) PCA Capture/Compare Model 4 16 bits Register               */
    __IO uint32_t  CARR;                         /*!< (@ 0x00000074) PCA Auto-reload Register                                   */     
} PCA_TypeDef;                                   /*!< Size = 116 (0x78)                                                         */


/**
  * @brief Power Control
  */

typedef struct
{
    __IO uint32_t WPR;     /*!< PWR Write protect register,         Address offset: 0x00 */
    __IO uint32_t CR1;     /*!< PWR power control1 register,        Address offset: 0x04 */
    __IO uint32_t CR2;     /*!< PWR power control2 register,        Address offset: 0x08 */
    __IO uint32_t CR3;     /*!< PWR power control2 register,        Address offset: 0x0C */
         uint32_t RESERVED[8];
    __IO uint32_t LVD_CR;  /*!< LVD control register,               Address offset: 0x30 */
    __IO uint32_t LVD_SR;  /*!< LVD status register,                Address offset: 0x34 */
} PWR_TypeDef;

/**
  * @brief Clock Control
  */
typedef struct
{
    __IO uint32_t CSR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
    __IO uint32_t ICSCR;       /*!< RCC clock internal clock source calibrate register,          Address offset: 0x04 */
    __IO uint32_t CFGR;        /*!< RCC clock configuration register,                            Address offset: 0x08 */
    __IO uint32_t PERIENR;     /*!< RCC peripheral clock configuration register                  Address offset: 0x0C */
    __IO uint32_t LCSR;        /*!< RCC LSI clock control register,                              Address offset: 0x10 */
    __IO uint32_t LCSCR;       /*!< LSI clock calibrate register,                                Address offset: 0x14 */
    __IO uint32_t PERIRSTR;    /*!< RCC peripheral reset register,                               Address offset: 0x18 */
    __IO uint32_t RSTRINFO;    /*!< RCC Reset flag information register,                         Address offset: 0x1C */
    __IO uint32_t RSTRCR;      /*!< RCC Reset option byte reload register,                       Address offset: 0x20 */
} RCC_TypeDef;


/**
  * @brief Real-Time Clock
  */

typedef struct
{
    __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
    __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
    __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
    __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
    __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
    __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
    uint32_t RESERVED0;    /*!< Reserved register,                                        Address offset: 0x18 */
    __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
    uint32_t RESERVED1;    /*!< Reserved register,                                        Address offset: 0x20 */
    __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
    __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
    __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
    uint32_t RESERVED2;    /*!< Reserved register,                                        Address offset: 0x30 */
    uint32_t RESERVED3;    /*!< Reserved register,                                        Address offset: 0x34 */
    uint32_t RESERVED4;    /*!< Reserved register,                                        Address offset: 0x38 */
    __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
    uint32_t RESERVED5;    /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
    __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
    uint32_t RESERVED6;    /*!< Reserved,                                                 Address offset: 0x48 */
    uint32_t RESERVED7;    /*!< Reserved,                                                 Address offset: 0x4C */
    __IO uint32_t BKP0R;   /*!< RTC backup register 0,                                    Address offset: 0x50 */
} RTC_TypeDef;


/**
  * @brief Serial Peripheral Interface
  */

typedef struct
{
    __IO uint16_t CR1;      /*!< SPI Control register 1                       ,       Address offset: 0x00 */
    uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
    __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
    uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
    __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
    uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
    __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
    uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
    __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
    uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
    __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register ,                                Address offset: 0x14 */
    uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
    __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register ,                                Address offset: 0x18 */
    uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
} SPI_TypeDef;


/**
  * @brief SysTem Configuration
  */

typedef struct
{
    __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
    __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x04 */
    __IO uint32_t PORTCR;         /*!< SYSCFG Port interrupt configuration register,           Address offset: 0x08 */
    __IO uint32_t PCACR;          /*!< SYSCFG PCA interrupt configuration register,            Address offset: 0x0C */
    __IO uint32_t TIM1CR;         /*!< SYSCFG Time1 interrupt configuration register,          Address offset: 0x10 */
    __IO uint32_t TIM2CR;         /*!< SYSCFG Time2 interrupt configuration register,          Address offset: 0x14 */
} SYSCFG_TypeDef;


/**
  * @brief TIM
  */
typedef struct
{
    __IO uint16_t CR1;             /*!< TIM control register 1,                                     Address offset: 0x00 */
    uint16_t RESERVED0;            /*!< Reserved,                                                                   0x02 */
    __IO uint16_t CR2;             /*!< TIM control register 2,                                     Address offset: 0x04 */
    uint16_t RESERVED1;            /*!< Reserved,                                                                   0x06 */
    __IO uint16_t SMCR;            /*!< TIM slave Mode Control register(Except TIM4/5),             Address offset: 0x08 */
    uint16_t RESERVED2;            /*!< Reserved,                                                                   0x0A */
    __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,                          Address offset: 0x0C */
    uint16_t RESERVED3;            /*!< Reserved,                                                                   0x0E */
    __IO uint16_t SR;              /*!< TIM status register,                                        Address offset: 0x10 */
    uint16_t RESERVED4;            /*!< Reserved,                                                                   0x12 */
    __IO uint16_t EGR;             /*!< TIM event generation register,                              Address offset: 0x14 */
    uint16_t RESERVED5;            /*!< Reserved,                                                                   0x16 */
    __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1(Except TIM4/5),        Address offset: 0x18 */
    uint16_t RESERVED6;            /*!< Reserved,                                                                   0x1A */
    __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2(Except TIM4/5),        Address offset: 0x1C */
    uint16_t RESERVED7;            /*!< Reserved,                                                                   0x1E */
    __IO uint16_t CCER;            /*!< TIM capture/compare enable register(Except TIM4/5),         Address offset: 0x20 */
    uint16_t RESERVED8;            /*!< Reserved,                                                                   0x22 */
    __IO uint32_t CNT;             /*!< TIM counter register,                                       Address offset: 0x24 */
    __IO uint16_t PSC;             /*!< TIM prescaler register,                                     Address offset: 0x28 */
    uint16_t RESERVED9;            /*!< Reserved,                                                                   0x2A */
    __IO uint32_t ARR;             /*!< TIM auto-reload register,                                   Address offset: 0x2C */
    __IO uint16_t RCR;             /*!< TIM  repetition counter register(Except TIM4/5),            Address offset: 0x30 */
    uint16_t RESERVED10;           /*!< Reserved,                                                                   0x32 */
    __IO uint32_t CCR1;            /*!< TIM capture/compare register 1(Except TIM4/5),              Address offset: 0x34 */
    __IO uint32_t CCR2;            /*!< TIM capture/compare register 2(Except TIM4/5),              Address offset: 0x38 */
    __IO uint32_t CCR3;            /*!< TIM capture/compare register 3(Except TIM4/5),              Address offset: 0x3C */
    __IO uint32_t CCR4;            /*!< TIM capture/compare register 4(Except TIM4/5),              Address offset: 0x40 */
    __IO uint16_t BDTR;            /*!< TIM break and dead-time register(Except TIM4/5),            Address offset: 0x44 */
    uint16_t RESERVED11;           /*!< Reserved,                                                                   0x46 */
    __IO uint16_t DCR;             /*!< TIM DMA control register(Except TIM4/5),                    Address offset: 0x48 */
    uint16_t RESERVED12;           /*!< Reserved,                                                                   0x4A */
    __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register(Except TIM4/5),  Address offset: 0x4C */
    uint16_t RESERVED13;           /*!< Reserved,                                                                   0x4E */
    __IO uint16_t OR;              /*!< TIM option register(Except TIM4/5),                         Address offset: 0x50 */
    uint16_t RESERVED14;           /*!< Reserved,                                                                   0x52 */
} TIM_TypeDef;

/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */

typedef struct
{
    __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
    uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
    __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
    uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
    __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
    uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
    __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
    uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
    __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
    uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
    __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
    uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
    __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
    uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
} USART_TypeDef;


/**
  * @brief WINDOWS WATCHDOG
  */
typedef struct
{
    __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
    __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
    __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
} WWDG_TypeDef;



/**
  * @}
  */

/** @addtogroup Peripheral_memory_map
  * @{
  */
#define UID_INDEX1_BASE        ((uint32_t)0x1FFFFD00U) /*!< Unique device ID1 register 32bits base address    */
#define UID_INDEX2_BASE        ((uint32_t)0x1FFFFD04U) /*!< Unique device ID2 register 32bits base address  */
#define UID_INDEX3_BASE        ((uint32_t)0x1FFFFD08U) /*!< Unique device ID3 register 32bits base address     */
#define UID_INDEX4_BASE        ((uint32_t)0x1FFFFD0CU) /*!< Unique device ID4 register 32bits base address     */
#define LDO_ULP_BASE           ((uint32_t)0x1FFFFC04U) /*!< ULP LDO output volatge value base address             */
#define LDO_MOFF_BASE          ((uint32_t)0x1FFFFC08U) /*!< MOFF LDO output volatge value base address            */
#define LDO_VREF_BASE          ((uint32_t)0x1FFFFC0CU) /*!< Vref reference value base address                     */
#define RC32K_BASE             ((uint32_t)0x1FFFFC10U) /*!< 32768 RCL calibration value base address              */
#define RC4M_BASE              ((uint32_t)0x1FFFFC14U) /*!< 4M RCH calibration value base address  at 25 degree Celsius*/
#define RC16M_BASE             ((uint32_t)0x1FFFFC18U) /*!< 16M RCH calibration value base address  at 25 degree Celsius*/
#define RC24M_BASE             ((uint32_t)0x1FFFFC1CU) /*!< 24M RCH calibration value base address  at 25 degree Celsius*/
#define ADC_OFFSET_BASE        ((uint32_t)0x1FFFFC20U) /*!< Adc Calibration offset base address                   */
#define VCAP_STEP_BASE         ((uint32_t)0x1FFFFC24U) /*!< Adc Vcap step base address                            */


#define OB_BASE                ((uint32_t)0x1FFFFE00U) /*!< FLASH Option Bytes base address */
#define FLASH_BASE             ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
#define FLASH_END              ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
#define SRAM_BASE              ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
#define SRAM_SIZE_MAX          ((uint32_t)0x00001000U) /*!< maximum SRAM size (up to 4KBytes) */

#define PERIPH_BASE            ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */

/*****<TC32L010 peripheral memory map>****/

/*!< Peripheral memory map */
#define APBPERIPH_BASE         (PERIPH_BASE)
#define AHBPERIPH_BASE         (PERIPH_BASE + 0x00020000U)
#define IOPERIPH_BASE          (PERIPH_BASE + 0x00021000U)

/*!< APB peripherals */
#define USART0_BASE            (APBPERIPH_BASE)
#define USART1_BASE            (APBPERIPH_BASE + 0x00000400U)
#define SPI_BASE               (APBPERIPH_BASE + 0x00000800U)
#define I2C_BASE               (APBPERIPH_BASE + 0x00000C00U)
#define TIM1_BASE              (APBPERIPH_BASE + 0x00001000U)
#define PCA_BASE               (APBPERIPH_BASE + 0x00001400U)
#define TIM4_BASE              (APBPERIPH_BASE + 0x00001800U)
#define TIM5_BASE              (APBPERIPH_BASE + 0x00001900U)
#define SYSCFG_BASE            (APBPERIPH_BASE + 0x00001C00U)
#define WWDG_BASE              (APBPERIPH_BASE + 0x00002000U)
#define IWDG_BASE              (APBPERIPH_BASE + 0x00002400U)
#define ADC_BASE               (APBPERIPH_BASE + 0x00002C00U)
#define RTC_BASE               (APBPERIPH_BASE + 0x00003000U)
#define TIM2_BASE              (APBPERIPH_BASE + 0x00003C00U)
#define PWR_BASE               (APBPERIPH_BASE + 0x00004000U)
#define LPTIM_BASE             (APBPERIPH_BASE + 0x00004400U)
#define LPUART_BASE            (APBPERIPH_BASE + 0x00005000U)


/*!< AHB peripherals */
#define RCC_BASE               (AHBPERIPH_BASE)
#define FLASH_R_BASE           (AHBPERIPH_BASE + 0x00000400U)
#define CRC_BASE               (AHBPERIPH_BASE + 0x00000800U)
#define DMA_BASE               (AHBPERIPH_BASE + 0x00000C00U)
#define DMA_Channel1_BASE      (DMA_BASE + 0x00000008U)
#define DMA_Channel2_BASE      (DMA_BASE + 0x0000001CU)
/*!< IO peripherals */
#define GPIOA_BASE             (IOPERIPH_BASE)
#define GPIOB_BASE             (IOPERIPH_BASE + 0x00000400U)
#define GPIOC_BASE             (IOPERIPH_BASE + 0x00000800U)
#define GPIOD_BASE             (IOPERIPH_BASE + 0x00000C00U)

#define FLASH                  ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB                     ((OB_TypeDef *) OB_BASE)
#define GPIOA                  ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                  ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC                  ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD                  ((GPIO_TypeDef *) GPIOD_BASE)
#define USART0                 ((USART_TypeDef *) USART0_BASE)
#define USART1                 ((USART_TypeDef *) USART1_BASE)
#define LPTIM0                 ((LPTIM_TypeDef *) LPTIM_BASE)
#define LPUART0                ((LPUART_TypeDef *) LPUART_BASE)
#define SPI0                   ((SPI_TypeDef *) SPI_BASE)
#define I2C0                   ((I2C_TypeDef *) I2C_BASE)
#define TIM1                   ((TIM_TypeDef *) TIM1_BASE)
#define TIM2                   ((TIM_TypeDef *) TIM2_BASE)
#define PCA                    ((PCA_TypeDef *) PCA_BASE)
#define TIM4                   ((TIM_TypeDef *) TIM4_BASE)
#define TIM5                   ((TIM_TypeDef *) TIM5_BASE)
#define RCC                    ((RCC_TypeDef *) RCC_BASE)
#define PWR                    ((PWR_TypeDef *) PWR_BASE)
#define RTC                    ((RTC_TypeDef *) RTC_BASE)
#define ADC1                   ((ADC_TypeDef *) ADC_BASE)
#define WWDG                   ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG                   ((IWDG_TypeDef *) IWDG_BASE)
#define CRC                    ((CRC_TypeDef *) CRC_BASE)
#define SYSCFG                 ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define DMA                    ((DMA_TypeDef *) DMA_BASE)
#define DMA_Channel1           ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
#define DMA_Channel2           ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)

/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/

/******************************************************************************/
/*                         Peripheral Registers Bits Definition               */
/******************************************************************************/
/******************************************************************************/
/*                                                                            */
/*                      Analog to Digital Converter (ADC)                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for ADC_CR0 register  ******************/
#define ADC_CR0_ADCEN                          ((uint32_t)0x00000001)
#define ADC_CR0_START                          ((uint32_t)0x00000002)

#define ADC_CR0_CHSEL                          ((uint32_t)0x00000700)
#define ADC_CR0_CHSEL_CH0                      ((uint32_t)0x00000000)
#define ADC_CR0_CHSEL_CH1                      ((uint32_t)0x00000100)
#define ADC_CR0_CHSEL_CH2                      ((uint32_t)0x00000200)
#define ADC_CR0_CHSEL_CH3                      ((uint32_t)0x00000300)
#define ADC_CR0_CHSEL_CH4                      ((uint32_t)0x00000400)
#define ADC_CR0_CHSEL_CH5                      ((uint32_t)0x00000500)
#define ADC_CR0_CHSEL_CH6                      ((uint32_t)0x00000600)
#define ADC_CR0_CHSEL_CH7                      ((uint32_t)0x00000700)

#define ADC_CR0_DISCARD                        ((uint32_t)0x00001000)

#define ADC_CR0_DISH                           ((uint32_t)0x00010000)
#define ADC_CR0_DISH_NORMAL                    ((uint32_t)0x00000000)
#define ADC_CR0_DISH_SHORT                     ((uint32_t)0x00010000)

#define ADC_CR0_RATIO                          ((uint32_t)0x00060000)
#define ADC_CR0_RATIO_12BIT                    ((uint32_t)0x00000000)
#define ADC_CR0_RATIO_10BIT                    ((uint32_t)0x00020000)

#define ADC_CR0_GCMP                           ((uint32_t)0x00080000)

#define ADC_CR0_OFFSET                         ((uint32_t)0x03F00000)

/********************  Bits definition for ADC_CR1 register  ******************/
#define ADC_CR1_TRIGS                          ((uint32_t)0x0000001F)
#define ADC_CR1_CT                             ((uint32_t)0x00000100)
#define ADC_CR1_CT_SINGLE                      ((uint32_t)0x00000000)
#define ADC_CR1_CT_CONTINUE                    ((uint32_t)0x00000100)
#define ADC_CR1_RACCEN                         ((uint32_t)0x00000200)
#define ADC_CR1_LTCMP                          ((uint32_t)0x00000400)
#define ADC_CR1_HTCMP                          ((uint32_t)0x00000800)
#define ADC_CR1_REGCMP                         ((uint32_t)0x00001000)
#define ADC_CR1_RACC_CLR                       ((uint32_t)0x00002000)

/********************  Bits definition for ADC_CR2 register  ******************/
#define ADC_CR2_CHEN                           ((uint32_t)0x000000FF)
#define ADC_CR2_CHEN0EN                        ((uint32_t)0x00000001)
#define ADC_CR2_CHEN1EN                        ((uint32_t)0x00000002)
#define ADC_CR2_CHEN2EN                        ((uint32_t)0x00000004)
#define ADC_CR2_CHEN3EN                        ((uint32_t)0x00000008)
#define ADC_CR2_CHEN4EN                        ((uint32_t)0x00000010)
#define ADC_CR2_CHEN5EN                        ((uint32_t)0x00000020)
#define ADC_CR2_CHEN6EN                        ((uint32_t)0x00000040)
#define ADC_CR2_CHEN7EN                        ((uint32_t)0x00000080)
#define ADC_CR2_ADCCNT                         ((uint32_t)0x0000FF00)
#define ADC_CR2_DMAEN                          ((uint32_t)0x00010000)
#define ADC_CR2_READY                          ((uint32_t)0x00020000)

/******************  Bits definition for ADC_RESULT0 register  ****************/
#define ADC_RESULT0_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT1 register  ****************/
#define ADC_RESULT1_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT2 register  ****************/
#define ADC_RESULT2_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT3 register  ****************/
#define ADC_RESULT3_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT4 register  ****************/
#define ADC_RESULT4_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT5 register  ****************/
#define ADC_RESULT5_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT6 register  ****************/
#define ADC_RESULT6_RESULT                     ((uint32_t)0x00000FFF)

/******************  Bits definition for ADC_RESULT7 register  ****************/
#define ADC_RESULT7_RESULT                     ((uint32_t)0x00000FFF)

/*******************  Bits definition for ADC_RESULT register  ****************/
#define ADC_RESULT_RESULT                      ((uint32_t)0x00000FFF)

/*****************  Bits definition for ADC_RESULT_ACC register  **************/
#define ADC_RESULT_ACC_RESULT                  ((uint32_t)0x000FFFFF)

/******************  Bits definition for ADC_THRESHOLD register  **************/
#define ADC_THRESHOLD_LT                       ((uint32_t)0x00000FFF)
#define ADC_THRESHOLD_HT                       ((uint32_t)0x0FFF0000)

/******************  Bits definition for ADC_INTEN register  ******************/
#define ADC_INTEN_ADCIEN                     ((uint32_t)0x000000FF)
#define ADC_INTEN_ADCIEN0                    ((uint32_t)0x00000001)
#define ADC_INTEN_ADCIEN1                    ((uint32_t)0x00000002)
#define ADC_INTEN_ADCIEN2                    ((uint32_t)0x00000004)
#define ADC_INTEN_ADCIEN3                    ((uint32_t)0x00000008)
#define ADC_INTEN_ADCIEN4                    ((uint32_t)0x00000010)
#define ADC_INTEN_ADCIEN5                    ((uint32_t)0x00000020)
#define ADC_INTEN_ADCIEN6                    ((uint32_t)0x00000040)
#define ADC_INTEN_ADCIEN7                    ((uint32_t)0x00000080)

#define ADC_INTEN_LLTIEN                     ((uint32_t)0x00000100)
#define ADC_INTEN_HHTIEN                     ((uint32_t)0x00000200)
#define ADC_INTEN_REGIEN                     ((uint32_t)0x00000400)
#define ADC_INTEN_CONTIEN                    ((uint32_t)0x00000800)

/*****************  Bits definition for ADC_RAWINTSR register  ***************/
#define ADC_RAWINTSR_ADCRIS                  ((uint32_t)0x000000FF)
#define ADC_RAWINTSR_ADCI0                   ((uint32_t)0x00000001)
#define ADC_RAWINTSR_ADCI1                   ((uint32_t)0x00000002)
#define ADC_RAWINTSR_ADCI2                   ((uint32_t)0x00000004)
#define ADC_RAWINTSR_ADCI3                   ((uint32_t)0x00000008)
#define ADC_RAWINTSR_ADCI4                   ((uint32_t)0x00000010)
#define ADC_RAWINTSR_ADCI5                   ((uint32_t)0x00000020)
#define ADC_RAWINTSR_ADCI6                   ((uint32_t)0x00000040)
#define ADC_RAWINTSR_ADCI7                   ((uint32_t)0x00000080)

#define ADC_RAWINTSR_LLT                     ((uint32_t)0x00000100)
#define ADC_RAWINTSR_HHT                     ((uint32_t)0x00000200)
#define ADC_RAWINTSR_REG                     ((uint32_t)0x00000400)
#define ADC_RAWINTSR_CONT                    ((uint32_t)0x00000800)

/*****************  Bits definition for ADC_MSKINTSR register  ***************/
#define ADC_MSKINTSR_ADCRIS                  ((uint32_t)0x000000FF)
#define ADC_MSKINTSR_ADCI0                   ((uint32_t)0x00000001)
#define ADC_MSKINTSR_ADCI1                   ((uint32_t)0x00000002)
#define ADC_MSKINTSR_ADCI2                   ((uint32_t)0x00000004)
#define ADC_MSKINTSR_ADCI3                   ((uint32_t)0x00000008)
#define ADC_MSKINTSR_ADCI4                   ((uint32_t)0x00000010)
#define ADC_MSKINTSR_ADCI5                   ((uint32_t)0x00000020)
#define ADC_MSKINTSR_ADCI6                   ((uint32_t)0x00000040)
#define ADC_MSKINTSR_ADCI7                   ((uint32_t)0x00000080)

#define ADC_MSKINTSR_LLT                     ((uint32_t)0x00000100)
#define ADC_MSKINTSR_HHT                     ((uint32_t)0x00000200)
#define ADC_MSKINTSR_REG                     ((uint32_t)0x00000400)
#define ADC_MSKINTSR_CONT                    ((uint32_t)0x00000800)

/*******************  Bits definition for ADC_TIME register  *****************/
#define ADC_TIME_FIRST_SAMPLE                ((uint32_t)0x0000000F)
#define ADC_TIME_BURST_SAMPLE                ((uint32_t)0x000000F0)
#define ADC_TIME_STARTUP_TIME                ((uint32_t)0x00007F00)


/******************************************************************************/
/*                                                                            */
/*                       CRC calculation unit (CRC)                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_RESULT register  *********************/
#define  CRC_RESULT_RESULT                   ((uint32_t)0x0000FFFF) /*!< RESULT register */
#define  CRC_RESULT_FLAG                     ((uint32_t)0x00010000) /*!< RESULT flag register */

/*******************  Bit definition for CRC_IDR register  ********************/
#define  CRC_DATA_DATA                       ((uint32_t)0xFFFFFFFF) /*!< data register bits */


/******************************************************************************/
/*                                                                            */
/*                           Debug MCU (DBGMCU)                               */
/*                                                                            */
/******************************************************************************/

/****************  Bit definition for DBGMCU_IDCODE register  *****************/
#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */

#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */

/******************  Bit definition for DBGMCU_CR register  *******************/
#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */


/******************************************************************************/
/*                                                                            */
/*                           DMA Controller (DMA)                             */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for DMA_ISR register  ********************/
#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */


/*******************  Bit definition for DMA_IFCR register  *******************/
#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */


/*******************  Bit definition for DMA_CCR register  ********************/
#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */

#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */

#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */

#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */

#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */

/******************  Bit definition for DMA_CNDTR register  *******************/
#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */

/******************  Bit definition for DMA_CPAR register  ********************/
#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */

/******************  Bit definition for DMA_CMAR register  ********************/
#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */

/******************  Bit definition for DMA_CSELR register  *********************/
#define  DMA_CSELR_ADC                        ((uint32_t)0x00000000)
#define  DMA_CSELR_CH1_SPI_RX                 ((uint32_t)0x00000001)
#define  DMA_CSELR_CH1_I2C_TX                 ((uint32_t)0x00000002)
#define  DMA_CSELR_CH1_USART0_TX              ((uint32_t)0x00000003)
#define  DMA_CSELR_CH1_USART1_TX              ((uint32_t)0x00000004)
#define  DMA_CSELR_CH1_LPUART_TX              ((uint32_t)0x00000005)
#define  DMA_CSELR_CH1_TIM1_CH1               ((uint32_t)0x00000006)
#define  DMA_CSELR_CH1_TIM1_CH2               ((uint32_t)0x00000007)
#define  DMA_CSELR_CH1_TIM1_CH3               ((uint32_t)0x00000008)
#define  DMA_CSELR_CH1_TIM1_CH4               ((uint32_t)0x00000009)
#define  DMA_CSELR_CH1_TIM1_TRIG              ((uint32_t)0x0000000A)
#define  DMA_CSELR_CH1_TIM1_COM               ((uint32_t)0x0000000A)
#define  DMA_CSELR_CH1_TIM1_UP                ((uint32_t)0x0000000A)
#define  DMA_CSELR_CH1_TIM2_CH1               ((uint32_t)0x0000000B)
#define  DMA_CSELR_CH1_TIM2_CH2               ((uint32_t)0x0000000C)
#define  DMA_CSELR_CH1_TIM2_CH3               ((uint32_t)0x0000000D)
#define  DMA_CSELR_CH1_TIM2_CH4               ((uint32_t)0x0000000E)
#define  DMA_CSELR_CH1_TIM2_UP                ((uint32_t)0x0000000E)
#define  DMA_CSELR_CH1_TIM2_TRIG              ((uint32_t)0x0000000E)
#define  DMA_CSELR_CH1_TIM4_UP                ((uint32_t)0x0000000F)

#define  DMA_CSELR_CH2_SPI_TX                 ((uint32_t)0x00000010)
#define  DMA_CSELR_CH2_I2C_RX                 ((uint32_t)0x00000020)
#define  DMA_CSELR_CH2_USART0_RX              ((uint32_t)0x00000030)
#define  DMA_CSELR_CH2_USART1_RX              ((uint32_t)0x00000040)
#define  DMA_CSELR_CH2_LPUART_RX              ((uint32_t)0x00000050)
#define  DMA_CSELR_CH2_TIM1_CH1               ((uint32_t)0x00000060)
#define  DMA_CSELR_CH2_TIM1_CH2               ((uint32_t)0x00000070)
#define  DMA_CSELR_CH2_TIM1_CH3               ((uint32_t)0x00000080)
#define  DMA_CSELR_CH2_TIM1_CH4               ((uint32_t)0x00000090)
#define  DMA_CSELR_CH2_TIM1_TRIG              ((uint32_t)0x000000A0)
#define  DMA_CSELR_CH2_TIM1_COM               ((uint32_t)0x000000A0)
#define  DMA_CSELR_CH2_TIM1_UP                ((uint32_t)0x000000A0)
#define  DMA_CSELR_CH2_TIM2_CH1               ((uint32_t)0x000000B0)
#define  DMA_CSELR_CH2_TIM2_CH2               ((uint32_t)0x000000C0)
#define  DMA_CSELR_CH2_TIM2_CH3               ((uint32_t)0x000000D0)
#define  DMA_CSELR_CH2_TIM2_CH4               ((uint32_t)0x000000E0)
#define  DMA_CSELR_CH2_TIM2_UP                ((uint32_t)0x000000E0)
#define  DMA_CSELR_CH2_TIM2_TRIG              ((uint32_t)0x000000E0)
#define  DMA_CSELR_CH2_TIM5_UP                ((uint32_t)0x000000F0)


/******************************************************************************/
/*                                                                            */
/*                      FLASH and Option Bytes Registers                      */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for FLASH_CR register  ******************/
#define  FLASH_CR_OP                         ((uint32_t)0x00000003)
#define  FLASH_CR_EOPIE                      ((uint32_t)0x00000004)
#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000008)
#define  FLASH_CR_READY                      ((uint32_t)0x00000010)
#define  FLASH_CR_BUSY                       ((uint32_t)0x00000020)
#define  FLASH_CR_DPD                        ((uint32_t)0x00000100)
#define  FLASH_CR_LOCK                       ((uint32_t)0x00000200)
#define  FLASH_CR_SUPERMODE                  ((uint32_t)0x00000400)

/******************  Bit definition for FLASH_IFR register  *******************/
#define  FLASH_IFR_RDPERR                    ((uint32_t)0x00000001)
#define  FLASH_IFR_WRPERR                    ((uint32_t)0x00000002)
#define  FLASH_IFR_EOP                       ((uint32_t)0x00000004)

/******************  Bit definition for FLASH_WRPR register  ******************/
#define  FLASH_WRPR_WRPR                     ((uint32_t)0xFFFFFFFF)

/*****************  Bit definition for FLASH_BYPASS register  *****************/
#define  FLASH_BYPASS_BYSEQ                  ((uint32_t)0xFFFFFFFF)

/*******************  Bits definition for FLASH_OPTCR register  ***************/
#define  FLASH_OPTCR_OBLERR                  ((uint32_t)0x00000001)
#define  FLASH_OPTCR_RDP                     ((uint32_t)0x00000020)
#define  FLASH_OPTCR_SWDP                    ((uint32_t)0x00000040)
#define  FLASH_OPTCR_ISPCON                  ((uint32_t)0x00000080)
#define  FLASH_OPTCR_USER                    ((uint32_t)0x0000FF00)
#define  FLASH_OPTCR_DATA0                   ((uint32_t)0x00FF0000)
#define  FLASH_OPTCR_DATA1                   ((uint32_t)0xFF000000)

/*****************  Bit definition for FLASH_DPDKEY register  *****************/
#define  FLASH_DPDKEY_DPDKEY                 ((uint32_t)0xFFFFFFFF)

/******************  Bit definition for FLASH_TIME register  ******************/
#define  FLASH_TIME_TIMMING                  ((uint32_t)0x0000001F)
#define  FLASH_TIME_POR_DPDCNT               ((uint32_t)0x00003F00)
#define  FLASH_TIME_CFHCNT                   ((uint32_t)0x00070000)
#define  FLASH_TIME_LATENCY                  ((uint32_t)0x01000000)
#define  FLASH_TIME_LVCTL                    ((uint32_t)0x02000000)


/******************************************************************************/
/*                                                                            */
/*                       General Purpose IOs (GPIO)                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for GPIO_DIRCR register  *****************/
#define  GPIO_DIRCR_PxDIRCR0                ((uint32_t)0x00000001)
#define  GPIO_DIRCR_PxDIRCR1                ((uint32_t)0x00000002)
#define  GPIO_DIRCR_PxDIRCR2                ((uint32_t)0x00000004)
#define  GPIO_DIRCR_PxDIRCR3                ((uint32_t)0x00000008)
#define  GPIO_DIRCR_PxDIRCR4                ((uint32_t)0x00000010)
#define  GPIO_DIRCR_PxDIRCR5                ((uint32_t)0x00000020)
#define  GPIO_DIRCR_PxDIRCR6                ((uint32_t)0x00000040)
#define  GPIO_DIRCR_PxDIRCR7                ((uint32_t)0x00000080)

/******************  Bit definition for GPIO_ODR register  ********************/
#define  GPIO_ODR_0                         ((uint32_t)0x00000001)
#define  GPIO_ODR_1                         ((uint32_t)0x00000002)
#define  GPIO_ODR_2                         ((uint32_t)0x00000004)
#define  GPIO_ODR_3                         ((uint32_t)0x00000008)
#define  GPIO_ODR_4                         ((uint32_t)0x00000010)
#define  GPIO_ODR_5                         ((uint32_t)0x00000020)
#define  GPIO_ODR_6                         ((uint32_t)0x00000040)
#define  GPIO_ODR_7                         ((uint32_t)0x00000080)

/*******************  Bit definition for GPIO_IDR register  *******************/
#define  GPIO_IDR_0                         ((uint32_t)0x00000001)
#define  GPIO_IDR_1                         ((uint32_t)0x00000002)
#define  GPIO_IDR_2                         ((uint32_t)0x00000004)
#define  GPIO_IDR_3                         ((uint32_t)0x00000008)
#define  GPIO_IDR_4                         ((uint32_t)0x00000010)
#define  GPIO_IDR_5                         ((uint32_t)0x00000020)
#define  GPIO_IDR_6                         ((uint32_t)0x00000040)
#define  GPIO_IDR_7                         ((uint32_t)0x00000080)

/******************  Bit definition for GPIO_INTEN register  ******************/
#define  GPIO_INTEN_PxIEN0			            ((uint32_t)0x00000001)
#define  GPIO_INTEN_PxIEN1			            ((uint32_t)0x00000002)
#define  GPIO_INTEN_PxIEN2			            ((uint32_t)0x00000004)
#define  GPIO_INTEN_PxIEN3			            ((uint32_t)0x00000008)
#define  GPIO_INTEN_PxIEN4			            ((uint32_t)0x00000010)
#define  GPIO_INTEN_PxIEN5			            ((uint32_t)0x00000020)
#define  GPIO_INTEN_PxIEN6			            ((uint32_t)0x00000040)
#define  GPIO_INTEN_PxIEN7			            ((uint32_t)0x00000080)

/****************  Bit definition for GPIO_RAWINTSR register  *****************/
#define  GPIO_RAWINTST_PxRIS0               ((uint32_t)0x00000001)
#define  GPIO_RAWINTST_PxRIS1               ((uint32_t)0x00000002)
#define  GPIO_RAWINTST_PxRIS2               ((uint32_t)0x00000004)
#define  GPIO_RAWINTST_PxRIS3               ((uint32_t)0x00000008)
#define  GPIO_RAWINTST_PxRIS4               ((uint32_t)0x00000010)
#define  GPIO_RAWINTST_PxRIS5               ((uint32_t)0x00000020)
#define  GPIO_RAWINTST_PxRIS6               ((uint32_t)0x00000040)
#define  GPIO_RAWINTST_PxRIS7               ((uint32_t)0x00000080)

/****************  Bit definition for GPIO_MSKINTSR register  ****************/
#define  GPIO_MSKINTSR_PxMIS0               ((uint32_t)0x00000001)
#define  GPIO_MSKINTSR_PxMIS1               ((uint32_t)0x00000002)
#define  GPIO_MSKINTSR_PxMIS2               ((uint32_t)0x00000004)
#define  GPIO_MSKINTSR_PxMIS3               ((uint32_t)0x00000008)
#define  GPIO_MSKINTSR_PxMIS4               ((uint32_t)0x00000010)
#define  GPIO_MSKINTSR_PxMIS5               ((uint32_t)0x00000020)
#define  GPIO_MSKINTSR_PxMIS6               ((uint32_t)0x00000040)
#define  GPIO_MSKINTSR_PxMIS7               ((uint32_t)0x00000080)

/*****************  Bit definition for GPIO_INTCLR register  *****************/
#define  GPIO_INTCLR_PxICLR0                ((uint32_t)0x00000001)
#define  GPIO_INTCLR_PxICLR1                ((uint32_t)0x00000002)
#define  GPIO_INTCLR_PxICLR2                ((uint32_t)0x00000004)
#define  GPIO_INTCLR_PxICLR3                ((uint32_t)0x00000008)
#define  GPIO_INTCLR_PxICLR4                ((uint32_t)0x00000010)
#define  GPIO_INTCLR_PxICLR5                ((uint32_t)0x00000020)
#define  GPIO_INTCLR_PxICLR6                ((uint32_t)0x00000040)
#define  GPIO_INTCLR_PxICLR7                ((uint32_t)0x00000080)

/***************  Bit definition for GPIO_INTTYPECR register  ****************/
#define  GPIO_INTTYPCR_PxITYPE0             ((uint32_t)0x00000001)
#define  GPIO_INTTYPCR_PxITYPE1             ((uint32_t)0x00000002)
#define  GPIO_INTTYPCR_PxITYPE2             ((uint32_t)0x00000004)
#define  GPIO_INTTYPCR_PxITYPE3             ((uint32_t)0x00000008)
#define  GPIO_INTTYPCR_PxITYPE4             ((uint32_t)0x00000010)
#define  GPIO_INTTYPCR_PxITYPE5             ((uint32_t)0x00000020)
#define  GPIO_INTTYPCR_PxITYPE6             ((uint32_t)0x00000040)
#define  GPIO_INTTYPCR_PxITYPE7             ((uint32_t)0x00000080)

/****************  Bit definition for GPIO_INTPOLCR register  ****************/
#define  GPIO_INTPOLCR_PxIVAL0              ((uint32_t)0x00000001)
#define  GPIO_INTPOLCR_PxIVAL1              ((uint32_t)0x00000002)
#define  GPIO_INTPOLCR_PxIVAL2              ((uint32_t)0x00000004)
#define  GPIO_INTPOLCR_PxIVAL3              ((uint32_t)0x00000008)
#define  GPIO_INTPOLCR_PxIVAL4              ((uint32_t)0x00000010)
#define  GPIO_INTPOLCR_PxIVAL5              ((uint32_t)0x00000020)
#define  GPIO_INTPOLCR_PxIVAL6              ((uint32_t)0x00000040)
#define  GPIO_INTPOLCR_PxIVAL7              ((uint32_t)0x00000080)

/*****************  Bit definition for GPIO_INTANY register  *****************/
#define  GPIO_INTANY_PxIANY0                ((uint32_t)0x00000001)
#define  GPIO_INTANY_PxIANY1                ((uint32_t)0x00000002)
#define  GPIO_INTANY_PxIANY2                ((uint32_t)0x00000004)
#define  GPIO_INTANY_PxIANY3                ((uint32_t)0x00000008)
#define  GPIO_INTANY_PxIANY4                ((uint32_t)0x00000010)
#define  GPIO_INTANY_PxIANY5                ((uint32_t)0x00000020)
#define  GPIO_INTANY_PxIANY6                ((uint32_t)0x00000040)
#define  GPIO_INTANY_PxIANY7                ((uint32_t)0x00000080)

/*****************  Bit definition for GPIO_ODSET register  ******************/
#define  GPIO_ODSET_PxODSET0                ((uint32_t)0x00000001)
#define  GPIO_ODSET_PxODSET1                ((uint32_t)0x00000002)
#define  GPIO_ODSET_PxODSET2                ((uint32_t)0x00000004)
#define  GPIO_ODSET_PxODSET3                ((uint32_t)0x00000008)
#define  GPIO_ODSET_PxODSET4                ((uint32_t)0x00000010)
#define  GPIO_ODSET_PxODSET5                ((uint32_t)0x00000020)
#define  GPIO_ODSET_PxODSET6                ((uint32_t)0x00000040)
#define  GPIO_ODSET_PxODSET7                ((uint32_t)0x00000080)

/*****************  Bit definition for GPIO_ODCLR register  ******************/
#define  GPIO_ODCLR_PxODCLR0                ((uint32_t)0x00000001)
#define  GPIO_ODCLR_PxODCLR1                ((uint32_t)0x00000002)
#define  GPIO_ODCLR_PxODCLR2                ((uint32_t)0x00000004)
#define  GPIO_ODCLR_PxODCLR3                ((uint32_t)0x00000008)
#define  GPIO_ODCLR_PxODCLR4                ((uint32_t)0x00000010)
#define  GPIO_ODCLR_PxODCLR5                ((uint32_t)0x00000020)
#define  GPIO_ODCLR_PxODCLR6                ((uint32_t)0x00000040)
#define  GPIO_ODCLR_PxODCLR7                ((uint32_t)0x00000080)

/******************  Bit definition for GPIO_DBR register  *******************/
#define  GPIO_DBR_PxDBR0                    ((uint32_t)0x00000001)
#define  GPIO_DBR_PxDBR1                    ((uint32_t)0x00000002)
#define  GPIO_DBR_PxDBR2                    ((uint32_t)0x00000004)
#define  GPIO_DBR_PxDBR3                    ((uint32_t)0x00000008)
#define  GPIO_DBR_PxDBR4                    ((uint32_t)0x00000010)
#define  GPIO_DBR_PxDBR5                    ((uint32_t)0x00000020)
#define  GPIO_DBR_PxDBR6                    ((uint32_t)0x00000040)
#define  GPIO_DBR_PxDBR7                    ((uint32_t)0x00000080)

/*******************  Bit definition for GPIO_PUPDR register ******************/
#define  GPIO_PUPDR_PxPUPD0                 ((uint32_t)0x00000003)
#define  GPIO_PUPDR_PxPUPD1                 ((uint32_t)0x0000000C)
#define  GPIO_PUPDR_PxPUPD2                 ((uint32_t)0x00000030)
#define  GPIO_PUPDR_PxPUPD3                 ((uint32_t)0x000000C0)
#define  GPIO_PUPDR_PxPUPD4                 ((uint32_t)0x00000300)
#define  GPIO_PUPDR_PxPUPD5                 ((uint32_t)0x00000C00)
#define  GPIO_PUPDR_PxPUPD6                 ((uint32_t)0x00003000)
#define  GPIO_PUPDR_PxPUPD7                 ((uint32_t)0x0000C000)

/*******************  Bit definition for GPIO_DRVCR register *****************/
#define  GPIO_DRVCR_PxDRV0                  ((uint32_t)0x00000003)
#define  GPIO_DRVCR_PxDRV1                  ((uint32_t)0x0000000C)
#define  GPIO_DRVCR_PxDRV2                  ((uint32_t)0x00000030)
#define  GPIO_DRVCR_PxDRV3                  ((uint32_t)0x000000C0)
#define  GPIO_DRVCR_PxDRV4                  ((uint32_t)0x00000300)
#define  GPIO_DRVCR_PxDRV5                  ((uint32_t)0x00000C00)
#define  GPIO_DRVCR_PxDRV6                  ((uint32_t)0x00003000)
#define  GPIO_DRVCR_PxDRV7                  ((uint32_t)0x0000C000)

/********************  Bit definition for GPIO_AFR register ******************/
#define  GPIO_AFR_PxAFR0                    ((uint32_t)0x0000000F)
#define  GPIO_AFR_PxAFR1                    ((uint32_t)0x000000F0)
#define  GPIO_AFR_PxAFR2                    ((uint32_t)0x00000F00)
#define  GPIO_AFR_PxAFR3                    ((uint32_t)0x0000F000)
#define  GPIO_AFR_PxAFR4                    ((uint32_t)0x000F0000)
#define  GPIO_AFR_PxAFR5                    ((uint32_t)0x00F00000)
#define  GPIO_AFR_PxAFR6                    ((uint32_t)0x0F000000)
#define  GPIO_AFR_PxAFR7                    ((uint32_t)0xF0000000)

/******************  Bit definition for GPIO_IS register  ********************/
#define  GPIO_IS_IS0                        ((uint32_t)0x00000001)
#define  GPIO_IS_IS1                        ((uint32_t)0x00000002)
#define  GPIO_IS_IS2                        ((uint32_t)0x00000004)
#define  GPIO_IS_IS3                        ((uint32_t)0x00000008)
#define  GPIO_IS_IS4                        ((uint32_t)0x00000010)
#define  GPIO_IS_IS5                        ((uint32_t)0x00000020)
#define  GPIO_IS_IS6                        ((uint32_t)0x00000040)
#define  GPIO_IS_IS7                        ((uint32_t)0x00000080)


/******************************************************************************/
/*                                                                            */
/*                   Inter-integrated Circuit Interface (I2C)                 */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for I2C_CON register  ********************/
#define  I2C_CON_MASTER_MODE                ((uint32_t)0x00000001)        
#define  I2C_CON_SPEED                      ((uint32_t)0x00000002)   
#define  I2C_CON_SPEED_100K                 ((uint32_t)0x00000000)   
#define  I2C_CON_SPEED_400K                 ((uint32_t)0x00000002)   
#define  I2C_CON_10BITADDR                  ((uint32_t)0x00000010)
#define  I2C_CON_RESTART_EN                 ((uint32_t)0x00000020)
#define  I2C_CON_STOP_DET                   ((uint32_t)0x00000080)
#define  I2C_CON_TX_EMPTY_IE                ((uint32_t)0x00000100)
#define  I2C_CON_RX_FIFOFULL_HLD            ((uint32_t)0x00000200)
#define  I2C_CON_ACK_GENNERALCALL           ((uint32_t)0x00000400)        

/******************  Bit definition for I2C_TAR register  ********************/     
#define  I2C_TAR_TAR                        ((uint32_t)0x000003FF)                         
#define  I2C_TAR_GC_OR_START                ((uint32_t)0x00000400)                         
#define  I2C_TAR_SPECIAL                    ((uint32_t)0x00000800)                         

/******************  Bit definition for I2C_SAR register  ********************/     
#define  I2C_SAR_SAR                        ((uint32_t)0x000003FF)                         

/*******************  Bit definition for I2C_DATA_CMD register  ********************/
#define  I2C_DATACMD_DAT                    ((uint32_t)0x000000FF)
#define  I2C_DATACMD_CMD                    ((uint32_t)0x00000100)
#define  I2C_DATACMD_STOP                   ((uint32_t)0x00000200)
#define  I2C_DATACMD_RESTART                ((uint32_t)0x00000400)

/********************  Bit definition for I2C_SCL_CNT register  ********************/
#define  I2C_SCL_CNT_H                      ((uint32_t)0x000001FF)                      
#define  I2C_SCL_CNT_L                      ((uint32_t)0x01FF0000)                     

/*******************  Bit definition for I2C_INTR_STAT register ********************/
#define  I2C_INTR_STAT_RXUNDER              ((uint32_t)0x00000001)               
#define  I2C_INTR_STAT_RXOVER               ((uint32_t)0x00000002)                 
#define  I2C_INTR_STAT_RXFULL               ((uint32_t)0x00000004)                  
#define  I2C_INTR_STAT_TXOVER               ((uint32_t)0x00000008) 
#define  I2C_INTR_STAT_TXEMPTY              ((uint32_t)0x00000010)  
#define  I2C_INTR_STAT_RDREQ                ((uint32_t)0x00000020)  
#define  I2C_INTR_STAT_TXABRT               ((uint32_t)0x00000040)  
#define  I2C_INTR_STAT_RXDONE               ((uint32_t)0x00000080)  
#define  I2C_INTR_STAT_ACTIVITY             ((uint32_t)0x00000100)  
#define  I2C_INTR_STAT_STOPDET              ((uint32_t)0x00000200)  
#define  I2C_INTR_STAT_STARTDET             ((uint32_t)0x00000400)  
#define  I2C_INTR_STAT_GENCALL              ((uint32_t)0x00000800)

/******************* Bit definition for I2C_INTR_MASK register ********************/
#define  I2C_INTR_MASK_RXUNDER              ((uint32_t)0x00000001)                
#define  I2C_INTR_MASK_RXOVER               ((uint32_t)0x00000002)                 
#define  I2C_INTR_MASK_RXFULL               ((uint32_t)0x00000004)                 
#define  I2C_INTR_MASK_TXOVER               ((uint32_t)0x00000008) 
#define  I2C_INTR_MASK_TXEMPTY              ((uint32_t)0x00000010) 
#define  I2C_INTR_MASK_RDREQ                ((uint32_t)0x00000020) 
#define  I2C_INTR_MASK_TXABRT               ((uint32_t)0x00000040) 
#define  I2C_INTR_MASK_RXDONE               ((uint32_t)0x00000080) 
#define  I2C_INTR_MASK_ACTIVITY             ((uint32_t)0x00000100) 
#define  I2C_INTR_MASK_STOPDET              ((uint32_t)0x00000200) 
#define  I2C_INTR_MASK_STARTDET             ((uint32_t)0x00000400)
#define  I2C_INTR_MASK_GENCALL              ((uint32_t)0x00000800)  

/******************  Bit definition for I2C_INTR_CLR register  *********************/
#define  I2C_INTR_CLR_RXUNDER               ((uint32_t)0x00000001)                
#define  I2C_INTR_CLR_RXOVER                ((uint32_t)0x00000002)                 
#define  I2C_INTR_CLR_TXOVER                ((uint32_t)0x00000008) 
#define  I2C_INTR_CLR_RDREQ                 ((uint32_t)0x00000020) 
#define  I2C_INTR_CLR_TXABRT                ((uint32_t)0x00000040) 
#define  I2C_INTR_CLR_RXDONE                ((uint32_t)0x00000080) 
#define  I2C_INTR_CLR_ACTIVITY              ((uint32_t)0x00000100) 
#define  I2C_INTR_CLR_STOPDET               ((uint32_t)0x00000200) 
#define  I2C_INTR_CLR_STARTDET              ((uint32_t)0x00000400)
#define  I2C_INTR_CLR_GENCALL               ((uint32_t)0x00000800)  
#define  I2C_INTR_CLR_ALL                   ((uint32_t)0x00010000)

/******************  Bit definition for I2C_STATUS register  **********************/
#define  I2C_STATUS_ACTIVITY                ((uint32_t)0x00000001)                     
#define  I2C_STATUS_TFNF                    ((uint32_t)0x00000002)                     
#define  I2C_STATUS_TFE                     ((uint32_t)0x00000004)                       
#define  I2C_STATUS_RFNE                    ((uint32_t)0x00000008)                      
#define  I2C_STATUS_RFF                     ((uint32_t)0x00000010)                                         

/*******************  Bit definition for I2C_SDA_SETUP register  ******************/
#define  I2C_SDA_SETUP_SETUP                ((uint32_t)0x0000000F)        
#define  I2C_SDA_SETUP_HOLD                 ((uint32_t)0x001F0000)        

/******************  Bit definition for I2C_TXABRT register  **********************/
#define  I2C_TXABRT_7BADDRNOACK             ((uint32_t)0x00000001)
#define  I2C_TXABRT_10BADDR1NOACK           ((uint32_t)0x00000002)   
#define  I2C_TXABRT_10BADDR2NOACK           ((uint32_t)0x00000004)
#define  I2C_TXABRT_TXDATANOACK             ((uint32_t)0x00000008)
#define  I2C_TXABRT_GCALLNOACK              ((uint32_t)0x00000010)
#define  I2C_TXABRT_GCALLREAD               ((uint32_t)0x00000020)      
#define  I2C_TXABRT_SBYTEACKDET             ((uint32_t)0x00000080)                   
#define  I2C_TXABRT_SBYTENORSTRT            ((uint32_t)0x00000200)                   
#define  I2C_TXABRT_10BRDNORSTRT            ((uint32_t)0x00000400)
#define  I2C_TXABRT_MASTERDIS               ((uint32_t)0x00000800)
#define  I2C_TXABRT_LOST                    ((uint32_t)0x00001000)                      
#define  I2C_TXABRT_SLVFLUSHTXFIFO          ((uint32_t)0x00002000)
#define  I2C_TXABRT_SLVARBLOST              ((uint32_t)0x00004000)
#define  I2C_TXABRT_SLVRDINTX               ((uint32_t)0x00008000)
#define  I2C_TXABRT_USERABRT                ((uint32_t)0x00010000)

/*****************  Bit definition for I2C_ACK_FS_SPKLEN register  ****************/
#define  I2C_FS_SPKLEN                      ((uint32_t)0x00000007)        

/******************  Bit definition for I2C_ENABLE register  **********************/
#define  I2C_ENABLE_ENABLE                  ((uint32_t)0x00000001)   
#define  I2C_ENABLE_ABORT                   ((uint32_t)0x00000002)   

/***************** Bit definition for I2C_INTR_RAWSTAT register ******************/
#define  I2C_INTR_RAWSTAT_RXUNDER           ((uint32_t)0x00000001)               
#define  I2C_INTR_RAWSTAT_RXOVER            ((uint32_t)0x00000002)                 
#define  I2C_INTR_RAWSTAT_RXFULL            ((uint32_t)0x00000004)                  
#define  I2C_INTR_RAWSTAT_TXOVER            ((uint32_t)0x00000008) 
#define  I2C_INTR_RAWSTAT_TXEMPTY           ((uint32_t)0x00000010)  
#define  I2C_INTR_RAWSTAT_RDREQ             ((uint32_t)0x00000020)  
#define  I2C_INTR_RAWSTAT_TXABRT            ((uint32_t)0x00000040)  
#define  I2C_INTR_RAWSTAT_RXDONE            ((uint32_t)0x00000080)  
#define  I2C_INTR_RAWSTAT_ACTIVITY          ((uint32_t)0x00000100)  
#define  I2C_INTR_RAWSTAT_STOPDET           ((uint32_t)0x00000200)  
#define  I2C_INTR_RAWSTAT_STARTDET          ((uint32_t)0x00000400)  
#define  I2C_INTR_RAWSTAT_GENCALL           ((uint32_t)0x00000800)

/********************  Bit definition for I2C_DMA_CR register  ********************/
#define  I2C_DMA_CR_RDMAE                   ((uint32_t)0x00000001)        
#define  I2C_DMA_CR_TDMAE                   ((uint32_t)0x00000002)  

/*******************  Bit definition for I2C_DMA_TDLR register  *******************/
#define  I2C_DMA_TDLR                       ((uint32_t)0x00000001)        

/*******************  Bit definition for I2C_DMA_RDLR register  *******************/
#define  I2C_DMA_RDLR                       ((uint32_t)0x00000001)        


/******************************************************************************/
/*                                                                            */
/*                        Independent WATCHDOG (IWDG)                         */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IWDG_KR register  ********************/
#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */

/*******************  Bit definition for IWDG_PR register  ********************/
#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */

/*******************  Bit definition for IWDG_RLR register  *******************/
#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */

/*******************  Bit definition for IWDG_SR register  ********************/
#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */

/*******************  Bit definition for IWDG_KR register  ********************/
#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */


/******************************************************************************/
/*                                                                            */
/*                         Low Power Timer (LPTIM)                            */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for LPTIM_ISR register  *******************/
#define  LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match                       */
#define  LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match                    */
#define  LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event         */
#define  LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK          */
#define  LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK       */
#define  LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */
#define  LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */

/******************  Bit definition for LPTIM_ICR register  *******************/
#define  LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag                       */
#define  LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag                    */
#define  LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag         */
#define  LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag          */
#define  LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag       */
#define  LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */
#define  LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */

/******************  Bit definition for LPTIM_IER register ********************/
#define  LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable                       */
#define  LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable                    */
#define  LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable         */
#define  LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable          */
#define  LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable       */
#define  LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */
#define  LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */

/******************  Bit definition for LPTIM_CFGR register *******************/
#define  LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */

#define  LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */
#define  LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */
#define  LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */

#define  LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define  LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */
#define  LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */

#define  LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define  LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */
#define  LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */

#define  LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */
#define  LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */
#define  LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */
#define  LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */

#define  LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define  LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */
#define  LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */
#define  LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */

#define  LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define  LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */
#define  LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */

#define  LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable           */
#define  LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape          */
#define  LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */
#define  LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode         */
#define  LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable     */
#define  LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable     */

/******************  Bit definition for LPTIM_CR register  ********************/
#define  LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable                 */
#define  LPTIM_CR_SNGSTRT                       ((uint32_t)0x00000002)             /*!< Timer start in single mode     */
#define  LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */

/******************  Bit definition for LPTIM_CMP register  *******************/
#define  LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register     */

/******************  Bit definition for LPTIM_ARR register  *******************/
#define  LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */

/******************  Bit definition for LPTIM_CNT register  *******************/
#define  LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register     */


/******************************************************************************/
/*                                                                            */
/*                         Low Power Uart (LPUART)                            */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for LPUART_SR register  *******************/
#define  LPUART_SR_PE                           ((uint32_t)0x00000001)
#define  LPUART_SR_FE                           ((uint32_t)0x00000002)
#define  LPUART_SR_NE                           ((uint32_t)0x00000004)
#define  LPUART_SR_ORE                          ((uint32_t)0x00000008)
#define  LPUART_SR_IDLE                         ((uint32_t)0x00000010)
#define  LPUART_SR_RXNE                         ((uint32_t)0x00000020)
#define  LPUART_SR_TC                           ((uint32_t)0x00000040)
#define  LPUART_SR_TXE                          ((uint32_t)0x00000080)
#define  LPUART_SR_CTSIF                        ((uint32_t)0x00000200)
#define  LPUART_SR_CTS                          ((uint32_t)0x00000400)
#define  LPUART_SR_BUSY                         ((uint32_t)0x00010000)
#define  LPUART_SR_CMF                          ((uint32_t)0x00020000)
#define  LPUART_SR_WUF                          ((uint32_t)0x00100000)
#define  LPUART_SR_TEACK                        ((uint32_t)0x00200000)
#define  LPUART_SR_REACK                        ((uint32_t)0x00400000)

/******************  Bit definition for LPUART_DR register  *******************/
#define  LPUART_DR_DR                           ((uint32_t)0x000003FF)

/******************  Bit definition for LPUART_BRR register  ******************/
#define  LPUART_BRR_BRR                         ((uint32_t)0x000FFFFF)

/******************  Bit definition for LPUART_CR1 register  ******************/
#define  LPUART_CR1_SBK                         ((uint32_t)0x00000001)
#define  LPUART_CR1_RWU                         ((uint32_t)0x00000002)
#define  LPUART_CR1_RE                          ((uint32_t)0x00000004)
#define  LPUART_CR1_TE                          ((uint32_t)0x00000008)
#define  LPUART_CR1_IDLEIE                      ((uint32_t)0x00000010)
#define  LPUART_CR1_RXNEIE                      ((uint32_t)0x00000020)
#define  LPUART_CR1_TCIE                        ((uint32_t)0x00000040)
#define  LPUART_CR1_TXEIE                       ((uint32_t)0x00000080)
#define  LPUART_CR1_PEIE                        ((uint32_t)0x00000100)
#define  LPUART_CR1_PS                          ((uint32_t)0x00000200)
#define  LPUART_CR1_PCE                         ((uint32_t)0x00000400)
#define  LPUART_CR1_WAKE                        ((uint32_t)0x00000800)
#define  LPUART_CR1_M                           ((uint32_t)0x00001000)
#define  LPUART_CR1_UE                          ((uint32_t)0x00002000)
#define  LPUART_CR1_CMIE                        ((uint32_t)0x00004000)
#define  LPUART_CR1_DEDT                        ((uint32_t)0x001F0000)
#define  LPUART_CR1_DEAT                        ((uint32_t)0x03E00000)
#define  LPUART_CR1_UESM                        ((uint32_t)0x40000000)
//#define  LPUART_CR1_FLOAT                       ((uint32_t)0x80000000)

/******************  Bit definition for LPUART_CR2 register  ******************/
#define  LPUART_CR2_ADDM7                       ((uint32_t)0x00000010)
#define  LPUART_CR2_STOP                        ((uint32_t)0x00003000)
#define  LPUART_CR2_SWAP                        ((uint32_t)0x00008000)
#define  LPUART_CR2_RXINV                       ((uint32_t)0x00010000)
#define  LPUART_CR2_TXINV                       ((uint32_t)0x00020000)
#define  LPUART_CR2_DATAINV                     ((uint32_t)0x00040000)
#define  LPUART_CR2_MSBFIRST                    ((uint32_t)0x00080000)
#define  LPUART_CR2_ADDL                        ((uint32_t)0x0F000000)
#define  LPUART_CR2_ADDH                        ((uint32_t)0xF0000000)

/******************  Bit definition for LPUART_CR3 register  ******************/
#define  LPUART_CR3_EIE                         ((uint32_t)0x00000001)
#define  LPUART_CR3_HDSEL                       ((uint32_t)0x00000008)
#define  LPUART_CR3_DMAR                        ((uint32_t)0x00000020)
#define  LPUART_CR3_DMAT                        ((uint32_t)0x00000040)
#define  LPUART_CR3_RTSE                        ((uint32_t)0x00000100)
#define  LPUART_CR3_CTSE                        ((uint32_t)0x00000200)
#define  LPUART_CR3_CTSIE                       ((uint32_t)0x00000400)
#define  LPUART_CR3_OVRDIS                      ((uint32_t)0x00001000)
#define  LPUART_CR3_DEM                         ((uint32_t)0x00004000)
#define  LPUART_CR3_DEP                         ((uint32_t)0x00008000)
#define  LPUART_CR3_WUS                         ((uint32_t)0x00300000)
#define  LPUART_CR3_WUFIE                       ((uint32_t)0x00400000)


/******************************************************************************/
/*                                                                            */
/*                          Programmable Counter Array                        */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for PCA_CR register  *******************/
#define  PCA_CR_CCF0                            ((uint32_t)0x00000001)
#define  PCA_CR_CCF1                            ((uint32_t)0x00000002)
#define  PCA_CR_CCF2                            ((uint32_t)0x00000004)
#define  PCA_CR_CCF3                            ((uint32_t)0x00000008)
#define  PCA_CR_CCF4                            ((uint32_t)0x00000010)
#define  PCA_CR_CR                              ((uint32_t)0x00000040)
#define  PCA_CR_CF                              ((uint32_t)0x00000080)

/******************  Bit definition for PCA_MOD register  ******************/
#define  PCA_MOD_CFIE                           ((uint32_t)0x00000001)
#define  PCA_MOD_CPS                            ((uint32_t)0x0000000E)
#define  PCA_MOD_CPS_0                          ((uint32_t)0x00000000)
#define  PCA_MOD_CPS_1                          ((uint32_t)0x00000002)
#define  PCA_MOD_CPS_2                          ((uint32_t)0x00000004)
#define  PCA_MOD_CPS_3                          ((uint32_t)0x00000006)
#define  PCA_MOD_CPS_4                          ((uint32_t)0x00000008)
#define  PCA_MOD_CPS_5                          ((uint32_t)0x0000000A)
#define  PCA_MOD_CPS_6                          ((uint32_t)0x0000000C)
#define  PCA_MOD_CPS_7                          ((uint32_t)0x0000000E)
#define  PCA_MOD_CIDL                           ((uint32_t)0x00000010)

/******************  Bit definition for PCA_CNT register  ******************/
#define  PCA_CNT_CNT                            ((uint32_t)0x0000FFFF)

/*************  Bit definition for PCA_CCAPMx(0~4) register  ***************/
#define  PCA_CCAPMx_CCIE                        ((uint32_t)0x00000001)
#define  PCA_CCAPMx_PWM                         ((uint32_t)0x00000002)
#define  PCA_CCAPMx_TOG                         ((uint32_t)0x00000004)
#define  PCA_CCAPMx_MAT                         ((uint32_t)0x00000008)
#define  PCA_CCAPMx_CAPN                        ((uint32_t)0x00000010)
#define  PCA_CCAPMx_CAPP                        ((uint32_t)0x00000020)
#define  PCA_CCAPMx_ECOM                        ((uint32_t)0x00000040)
#define  PCA_CCAPMx_EPWM                        ((uint32_t)0x00000080)

/**********  Bit definition for PCA_CCAPxL_CCAP(0~4) register  ************/
#define  PCA_CCAPxL_CCAP                        ((uint32_t)0x000000FF)

/**********  Bit definition for PCA_CCAPxH_CCAP(0~4) register  ************/
#define  PCA_CCAPxH_CCAP                        ((uint32_t)0x000000FF)

/***************  Bit definition for PCA_CCAPO register  ******************/
#define  PCA_CCAPO_CCAPO0                       ((uint32_t)0x00000001)
#define  PCA_CCAPO_CCAPO1                       ((uint32_t)0x00000002)
#define  PCA_CCAPO_CCAPO2                       ((uint32_t)0x00000004)
#define  PCA_CCAPO_CCAPO3                       ((uint32_t)0x00000008)
#define  PCA_CCAPO_CCAPO4                       ((uint32_t)0x00000010)

/****************  Bit definition for PCA_POCR register  ******************/
#define  PCA_POCR_POE0                          ((uint32_t)0x00000001)
#define  PCA_POCR_POE1                          ((uint32_t)0x00000002)
#define  PCA_POCR_POE2                          ((uint32_t)0x00000004)
#define  PCA_POCR_POE3                          ((uint32_t)0x00000008)
#define  PCA_POCR_POE4                          ((uint32_t)0x00000010)
#define  PCA_POCR_POINV0                        ((uint32_t)0x00000100)
#define  PCA_POCR_POINV1                        ((uint32_t)0x00000200)
#define  PCA_POCR_POINV2                        ((uint32_t)0x00000400)
#define  PCA_POCR_POINV3                        ((uint32_t)0x00000800)
#define  PCA_POCR_POINV4                        ((uint32_t)0x00001000)

/*************  Bit definition for PCA_CCAPx(0~4) register  ***************/
#define  PCA_CCAPx_CCAP                         ((uint32_t)0x0000FFFF)

/****************  Bit definition for PCA_CARR register  ******************/
#define  PCA_CARR_CARR                          ((uint32_t)0x0000FFFF)


/******************************************************************************/
/*                                                                            */
/*                             Power Control                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for PWR_WPR register  *******************/
#define  PWR_WPR_KEY                          ((uint32_t)0x000000FF)

/********************  Bit definition for PWR_CR1 register  *******************/
#define  PWR_CR1_LPMS                         ((uint32_t)0x00000003)
#define  PWR_CR1_DEEPSLEEP0                   ((uint32_t)0x00000000)
#define  PWR_CR1_DEEPSLEEP1                   ((uint32_t)0x00000001)
#define  PWR_CR1_DEEPSLEEP2                   ((uint32_t)0x00000002)
#define  PWR_CR1_LPVOS                        ((uint32_t)0x00000004)
#define  PWR_CR1_SRAM_RM                      ((uint32_t)0x00000008)
#define  PWR_CR1_VREF12_PD                    ((uint32_t)0x00000010)
#define  PWR_CR1_FLASH_PORB                   ((uint32_t)0x00000020)
#define  PWR_CR1_FLASH_DPD                    ((uint32_t)0x00000040)
#define  PWR_CR1_FLASH_PD                     ((uint32_t)0x00000080)
#define  PWR_CR1_LPR                          ((uint32_t)0x00000100)
#define  PWR_CR1_REGLPF                       ((uint32_t)0x00000200)
#define  PWR_CR1_MVOS                         ((uint32_t)0x00000400)
#define  PWR_CR1_LVOS                         ((uint32_t)0x00000800)
#define  PWR_CR1_ENVREF12                     ((uint32_t)0x00001000)

/********************  Bit definition for PWR_CR2 register  *******************/
#define  PWR_CR2_MLDO_H                       ((uint32_t)0x0000001F)
#define  PWR_CR2_MLDO_L                       ((uint32_t)0x00001F00)
#define  PWR_CR2_ULPLDO_H                     ((uint32_t)0x001F0000)
#define  PWR_CR2_ULPLDO_L                     ((uint32_t)0x1F000000)

/********************  Bit definition for PWR_CR3 register  *******************/
#define  PWR_CR3_MBGP                         ((uint32_t)0x0000000F)
#define  PWR_CR3_VREF12                       ((uint32_t)0x00000F00)

/*******************  Bit definition for LVD_CR register  ********************/
#define  LVD_CR_LVDEN                         ((uint32_t)0x00000001)
#define  LVD_CR_LVDACT                        ((uint32_t)0x00000002)
#define  LVD_CR_VCCSEL                        ((uint32_t)0x0000000C)
#define  LVD_CR_REFSEL                        ((uint32_t)0x00000070)
#define  LVD_CR_CTRLEN                        ((uint32_t)0x00000080)
#define  LVD_CR_FLTEN                         ((uint32_t)0x00000100)
#define  LVD_CR_FTEN                          ((uint32_t)0x00001000)
#define  LVD_CR_RTEN                          ((uint32_t)0x00002000)
#define  LVD_CR_HTEN                          ((uint32_t)0x00004000)
#define  LVD_CR_INTEN                         ((uint32_t)0x00008000)
#define  LVD_CR_FLTNUM                        ((uint32_t)0x03FF0000)

/*******************  Bit definition for LVD_SR register  ********************/
#define  LVD_SR_INTF                          ((uint32_t)0x00000001)
#define  LVD_SR_FILTER                        ((uint32_t)0x00000002)


/******************************************************************************/
/*                                                                            */
/*                         Reset and Clock Control                            */
/*                                                                            */
/******************************************************************************/

/********************  Bit definition for RCC_CSR register  *******************/
#define  RCC_CSR_HSIRANGE_24                 ((uint32_t)0x00000004)        
#define  RCC_CSR_HSIRANGE_4                  ((uint32_t)0x00000008)        

#define  RCC_CSR_HSION                       ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
#define  RCC_CSR_HSIRDY                      ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
#define  RCC_CSR_HSIRANGE                    ((uint32_t)0x0000000C)        /*!< Internal High Speed clock range */
#define  RCC_CSR_STARTUPHSI                  ((uint32_t)0x000000C0)        /*!< Internal High Speed clock startup time select */
#define  RCC_CSR_HSEON                       ((uint32_t)0x00000100)        /*!< External High Speed clock enable */
#define  RCC_CSR_HSERDY                      ((uint32_t)0x00000200)        /*!< External High Speed clock ready flag */
#define  RCC_CSR_STARTUPHSE                  ((uint32_t)0x00000C00)        /*!< External High Speed clock startup time select */
#define  RCC_CSR_HSEBYP                      ((uint32_t)0x00001000)        /*!< External High Speed clock bypass */
#define  RCC_CSR_HSEDRV                      ((uint32_t)0x0000E000)        /*!< External High Speed clock drive select */
#define  RCC_CSR_CSSON                       ((uint32_t)0x00010000)        /*!< Clock Security System enable */
#define  RCC_CSR_CSSHSEIE                    ((uint32_t)0x00020000)        /*!< Clock Security System interrupt enable */
#define  RCC_CSR_CSSHSEF                     ((uint32_t)0x00040000)        /*!< Clock Security System interrupt flag */
#define  RCC_CSR_CSSHSEC                     ((uint32_t)0x00080000)        /*!< Clock Security System clear interrupt flag */

/********************  Bit definition for RCC_ICSCR register  *****************/
#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x0000003F)
#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00000FC0)
#define  RCC_ICSCR_HSISEL                    ((uint32_t)0x00007000)        /*!< Internal High Speed clock select */
#define  RCC_ICSCR_HSECONFIG                 ((uint32_t)0x001F0000)  
#define  RCC_ICSCR_HSECCSNUM                 ((uint32_t)0xFF000000)

/*******************  Bit definition for RCC_CFGR register  *******************/
/* SW configuration */
#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
#define  RCC_CFGR_SW_LSI                     ((uint32_t)0x00000002)        /*!< LSI selected as system clock */
#define  RCC_CFGR_SW_LSE                     ((uint32_t)0x00000003)        /*!< LSE selected as system clock */

/* PPRE configuration */
#define  RCC_CFGR_PPRE                       ((uint32_t)0x0000000C)        /*!< PRE[1:0] bits (APB prescaler) */
#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< PCLK not divided */
#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000004)        /*!< PCLK divided by 2 */
#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000008)        /*!< PCLK divided by 4 */
#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x0000000C)        /*!< PCLK divided by 8 */

/* HPRE configuration */
#define  RCC_CFGR_HPRE                       ((uint32_t)0x00000070)        /*!< HPRE[2:0] bits (AHB prescaler) */
#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000010)        /*!< SYSCLK divided by 2 */
#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000020)        /*!< SYSCLK divided by 4 */
#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x00000030)        /*!< SYSCLK divided by 8 */
#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x00000040)        /*!< SYSCLK divided by 16 */
#define  RCC_CFGR_HPRE_DIV32                 ((uint32_t)0x00000050)        /*!< SYSCLK divided by 32 */
#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x00000060)        /*!< SYSCLK divided by 64 */
#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x00000070)        /*!< SYSCLK divided by 128 */

#define  RCC_CFGR_LPUARTSEL                  ((uint32_t)0x00000300)
#define  RCC_CFGR_LPUARTSEL_PCLK             ((uint32_t)0x00000000)
#define  RCC_CFGR_LPUARTSEL_LSE              ((uint32_t)0x00000200)
#define  RCC_CFGR_LPUARTSEL_LSI              ((uint32_t)0x00000300)

#define  RCC_CFGR_LPTIMSEL                   ((uint32_t)0x00000C00)
#define  RCC_CFGR_LPTIMSEL_PCLK              ((uint32_t)0x00000000)
#define  RCC_CFGR_LPTIMSEL_LSE               ((uint32_t)0x00000800)
#define  RCC_CFGR_LPTIMSEL_LSI               ((uint32_t)0x00000C00)

#define  RCC_CFGR_ADCPOL                     ((uint32_t)0x00002000)
/* ADCPRE configuration */
#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)
#define  RCC_CFGR_ADCPRE_DIV1                ((uint32_t)0x00000000)
#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00004000)
#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00008000)
#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)

/* MCOSEL configuration */
#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x00070000)
#define  RCC_CFGR_MCOSEL_NOCLK               ((uint32_t)0x00000000)
#define  RCC_CFGR_MCOSEL_SYSCLK              ((uint32_t)0x00010000)
#define  RCC_CFGR_MCOSEL_HSI                 ((uint32_t)0x00020000)
#define  RCC_CFGR_MCOSEL_HSE                 ((uint32_t)0x00030000)
#define  RCC_CFGR_MCOSEL_LSI                 ((uint32_t)0x00040000)
#define  RCC_CFGR_MCOSEL_LSE                 ((uint32_t)0x00050000)

#define  RCC_CFGR_MCOSEN                     ((uint32_t)0x00080000)
#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x00300000)        /*!< MCO prescaler  */
#define  RCC_CFGR_MCOPRE_DIV1                ((uint32_t)0x00000000)        /*!< MCO is divided by 1   */
#define  RCC_CFGR_MCOPRE_DIV2                ((uint32_t)0x00100000)        /*!< MCO is divided by 2   */
#define  RCC_CFGR_MCOPRE_DIV4                ((uint32_t)0x00200000)        /*!< MCO is divided by 4   */
#define  RCC_CFGR_MCOPRE_DIV8                ((uint32_t)0x00300000)        /*!< MCO is divided by 8   */

/*****************  Bit definition for RCC_APBENR register  ******************/
#define  RCC_APBENR_USART0EN                 ((uint32_t)0x00000001)
#define  RCC_APBENR_USART1EN                 ((uint32_t)0x00000002)
#define  RCC_APBENR_SPIEN                    ((uint32_t)0x00000004)
#define  RCC_APBENR_I2CEN                    ((uint32_t)0x00000008)
#define  RCC_APBENR_TIM1EN                   ((uint32_t)0x00000010)
#define  RCC_APBENR_TIM3EN                   ((uint32_t)0x00000020)
#define  RCC_APBENR_TIM4EN                   ((uint32_t)0x00000040)
#define  RCC_APBENR_TIM5EN                   ((uint32_t)0x00000080)
#define  RCC_APBENR_SYSCFGEN                 ((uint32_t)0x00000100)
#define  RCC_APBENR_WWDGEN                   ((uint32_t)0x00000200)
#define  RCC_APBENR_IWDGEN                   ((uint32_t)0x00000400)
#define  RCC_APBENR_RTCEN                    ((uint32_t)0x00000800)
#define  RCC_APBENR_ADCEN                    ((uint32_t)0x00001000)
#define  RCC_APBENR_TIM2EN                   ((uint32_t)0x00010000)
#define  RCC_APBENR_PWREN                    ((uint32_t)0x00020000)
#define  RCC_APBENR_LPTIMEN                  ((uint32_t)0x00040000)
#define  RCC_APBENR_LPUARTEN                 ((uint32_t)0x00080000)
/******************  Bit definition for RCC_AHBENR register  ******************/
#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x01000000)        /*!< GPIOA clock enable */
#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x02000000)        /*!< GPIOB clock enable */
#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x04000000)        /*!< GPIOC clock enable */
#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x08000000)        /*!< GPIOD clock enable */
#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x10000000)        /*!< CRC clock enable */
#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x20000000)        /*!< DMA clock enable */
#define  RCC_AHBENR_STCKEN                   ((uint32_t)0x40000000)        /*!< SYSTICK clock enable */
#define  RCC_AHBENR_FLASHEN                  ((uint32_t)0x80000000)        /*!< FLASH clock enable */

/*****************  Bit definition for RCC_LCSR register  *********************/
#define  RCC_LCSR_LSION                      ((uint32_t)0x00000001)
#define  RCC_LCSR_LSIRDY                     ((uint32_t)0x00000002)
#define  RCC_LCSR_STARTUPLSI                 ((uint32_t)0x0000000C)
#define  RCC_LCSR_LSEON                      ((uint32_t)0x00000100)
#define  RCC_LCSR_LSERDY                     ((uint32_t)0x00000200)
#define  RCC_LCSR_STARTUPLSE                 ((uint32_t)0x00000C00)
#define  RCC_LCSR_LSEBYP                     ((uint32_t)0x00001000)
#define  RCC_LCSR_LSEDRV                     ((uint32_t)0x0000E000)

#define  RCC_LCSR_RTCSEL                     ((uint32_t)0x00030000)
#define  RCC_LCSR_RTCSEL_LSE                 ((uint32_t)0x00010000)
#define  RCC_LCSR_RTCSEL_LSI                 ((uint32_t)0x00020000)
#define  RCC_LCSR_RTCSEL_HSE_DIV             ((uint32_t)0x00030000)

#define  RCC_LCSR_RTCEN                      ((uint32_t)0x00040000)
#define  RCC_LCSR_RTCRST                     ((uint32_t)0x00080000)
#define  RCC_LCSR_RTCPRE                     ((uint32_t)0x00700000)
#define  RCC_LCSR_RCCUNLOCK                  ((uint32_t)0x00800000)
#define  RCC_LCSR_CSSLSEON                   ((uint32_t)0x01000000)
#define  RCC_LCSR_CSSLSEIE                   ((uint32_t)0x02000000)
#define  RCC_LCSR_CSSLSED                    ((uint32_t)0x04000000)

/*****************  Bit definition for RCC_LCSCR register  ****************/
#define  RCC_LCSCR_LSITRIM                   ((uint32_t)0x0000000F)
#define  RCC_LCSCR_LSICAL                    ((uint32_t)0x000003F0)
#define  RCC_LCSCR_IOPSEL                    ((uint32_t)0x00002000)
#define  RCC_LCSCR_RTUNE                     ((uint32_t)0x0000C000)
#define  RCC_LCSCR_LSECNFG                   ((uint32_t)0x001F0000)

/*****************  Bit definition for RCC_APB2RSTR register  *****************/
#define  RCC_APBRSTR_USART0RST              ((uint32_t)0x00000001)        /*!< USART0 clock reset */
#define  RCC_APBRSTR_USART1RST              ((uint32_t)0x00000002)        /*!< USART1 clock reset */
#define  RCC_APBRSTR_SPIRST                 ((uint32_t)0x00000004)        /*!< SPI clock reset */
#define  RCC_APBRSTR_I2CRST                 ((uint32_t)0x00000008)        /*!< I2C clock reset */
#define  RCC_APBRSTR_TIM1RST                ((uint32_t)0x00000010)        /*!< TIM1 clock reset */
#define  RCC_APBRSTR_TIM3RST                ((uint32_t)0x00000020)        /*!< TIM3 clock reset */
#define  RCC_APBRSTR_TIM4RST                ((uint32_t)0x00000040)        /*!< Timer 4 clock reset */
#define  RCC_APBRSTR_TIM5RST                ((uint32_t)0x00000080)        /*!< Timer 5 clock reset */
#define  RCC_APBRSTR_SYSCFGRST              ((uint32_t)0x00000100)        /*!< SYSCONFIG clock reset */
#define  RCC_APBRSTR_WWDGRST                ((uint32_t)0x00000200)        /*!< Window Watchdog clock reset */
#define  RCC_APBRSTR_ADCRST                 ((uint32_t)0x00001000)        /*!< ADC clock reset */
#define  RCC_APBRSTR_TIM2RST                ((uint32_t)0x00010000)        /*!< TIM2 clock reset */
#define  RCC_APBRSTR_PWRRST                 ((uint32_t)0x00020000)        /*!< PWR clock reset */
#define  RCC_APBRSTR_LPTIMRST               ((uint32_t)0x00040000)        /*!< LPTimer clock reset */
#define  RCC_APBRSTR_LPUARTRST              ((uint32_t)0x00080000)        /*!< Lpusart clock reset */
/*******************  Bit definition for RCC_AHBRSTR register  ****************/
#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x01000000)         /*!< GPIOA clock reset */
#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x02000000)         /*!< GPIOB clock reset */
#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x04000000)         /*!< GPIOC clock reset */
#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x08000000)         /*!< GPIOD clock reset */
#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x10000000)         /*!< CRC clock reset */
#define  RCC_AHBRSTR_DMARST                  ((uint32_t)0x20000000)         /*!< DMA clock reset */
#define  RCC_AHBRSTR_FLASHRST                ((uint32_t)0x80000000)         /*!< FLASH clock reset */

/*****************  Bit definition for RCC_RSTRINFO register  *****************/
#define  RCC_RSTRINFO_PORRSTF                ((uint32_t)0x00000001)
#define  RCC_RSTRINFO_SFTRSTF                ((uint32_t)0x00000002)
#define  RCC_RSTRINFO_WWDGRSTF               ((uint32_t)0x00000004)
#define  RCC_RSTRINFO_LOCKUPSTF              ((uint32_t)0x00000008)
#define  RCC_RSTRINFO_PINRSTF                ((uint32_t)0x00000010)
#define  RCC_RSTRINFO_IWDGRSTF               ((uint32_t)0x00000020)
#define  RCC_RSTRINFO_LVDRSTF                ((uint32_t)0x00000040)
#define  RCC_RSTRINFO_RMVF                   ((uint32_t)0x00000100)

/*****************  Bit definition for RCC_RSTRINFO register  *****************/
#define  RCC_RSTRCR_OBLRST                   ((uint32_t)0x00000001)


/******************************************************************************/
/*                                                                            */
/*                           Real-Time Clock (RTC)                            */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RTC_TR register  *******************/
#define  RTC_TR_PM                           ((uint32_t)0x00400000)
#define  RTC_TR_HT                           ((uint32_t)0x00300000)
#define  RTC_TR_HT_0                         ((uint32_t)0x00100000)
#define  RTC_TR_HT_1                         ((uint32_t)0x00200000)
#define  RTC_TR_HU                           ((uint32_t)0x000F0000)
#define  RTC_TR_HU_0                         ((uint32_t)0x00010000)
#define  RTC_TR_HU_1                         ((uint32_t)0x00020000)
#define  RTC_TR_HU_2                         ((uint32_t)0x00040000)
#define  RTC_TR_HU_3                         ((uint32_t)0x00080000)
#define  RTC_TR_MNT                          ((uint32_t)0x00007000)
#define  RTC_TR_MNT_0                        ((uint32_t)0x00001000)
#define  RTC_TR_MNT_1                        ((uint32_t)0x00002000)
#define  RTC_TR_MNT_2                        ((uint32_t)0x00004000)
#define  RTC_TR_MNU                          ((uint32_t)0x00000F00)
#define  RTC_TR_MNU_0                        ((uint32_t)0x00000100)
#define  RTC_TR_MNU_1                        ((uint32_t)0x00000200)
#define  RTC_TR_MNU_2                        ((uint32_t)0x00000400)
#define  RTC_TR_MNU_3                        ((uint32_t)0x00000800)
#define  RTC_TR_ST                           ((uint32_t)0x00000070)
#define  RTC_TR_ST_0                         ((uint32_t)0x00000010)
#define  RTC_TR_ST_1                         ((uint32_t)0x00000020)
#define  RTC_TR_ST_2                         ((uint32_t)0x00000040)
#define  RTC_TR_SU                           ((uint32_t)0x0000000F)
#define  RTC_TR_SU_0                         ((uint32_t)0x00000001)
#define  RTC_TR_SU_1                         ((uint32_t)0x00000002)
#define  RTC_TR_SU_2                         ((uint32_t)0x00000004)
#define  RTC_TR_SU_3                         ((uint32_t)0x00000008)

/********************  Bits definition for RTC_DR register  *******************/
#define  RTC_DR_YT                           ((uint32_t)0x00F00000)
#define  RTC_DR_YT_0                         ((uint32_t)0x00100000)
#define  RTC_DR_YT_1                         ((uint32_t)0x00200000)
#define  RTC_DR_YT_2                         ((uint32_t)0x00400000)
#define  RTC_DR_YT_3                         ((uint32_t)0x00800000)
#define  RTC_DR_YU                           ((uint32_t)0x000F0000)
#define  RTC_DR_YU_0                         ((uint32_t)0x00010000)
#define  RTC_DR_YU_1                         ((uint32_t)0x00020000)
#define  RTC_DR_YU_2                         ((uint32_t)0x00040000)
#define  RTC_DR_YU_3                         ((uint32_t)0x00080000)
#define  RTC_DR_WDU                          ((uint32_t)0x0000E000)
#define  RTC_DR_WDU_0                        ((uint32_t)0x00002000)
#define  RTC_DR_WDU_1                        ((uint32_t)0x00004000)
#define  RTC_DR_WDU_2                        ((uint32_t)0x00008000)
#define  RTC_DR_MT                           ((uint32_t)0x00001000)
#define  RTC_DR_MU                           ((uint32_t)0x00000F00)
#define  RTC_DR_MU_0                         ((uint32_t)0x00000100)
#define  RTC_DR_MU_1                         ((uint32_t)0x00000200)
#define  RTC_DR_MU_2                         ((uint32_t)0x00000400)
#define  RTC_DR_MU_3                         ((uint32_t)0x00000800)
#define  RTC_DR_DT                           ((uint32_t)0x00000030)
#define  RTC_DR_DT_0                         ((uint32_t)0x00000010)
#define  RTC_DR_DT_1                         ((uint32_t)0x00000020)
#define  RTC_DR_DU                           ((uint32_t)0x0000000F)
#define  RTC_DR_DU_0                         ((uint32_t)0x00000001)
#define  RTC_DR_DU_1                         ((uint32_t)0x00000002)
#define  RTC_DR_DU_2                         ((uint32_t)0x00000004)
#define  RTC_DR_DU_3                         ((uint32_t)0x00000008)

/********************  Bits definition for RTC_CR register  *******************/
#define  RTC_CR_COE                          ((uint32_t)0x00800000)
#define  RTC_CR_OSEL                         ((uint32_t)0x00600000)
#define  RTC_CR_OSEL_0                       ((uint32_t)0x00200000)
#define  RTC_CR_OSEL_1                       ((uint32_t)0x00400000)
#define  RTC_CR_POL                          ((uint32_t)0x00100000)
#define  RTC_CR_COSEL                        ((uint32_t)0x00080000)
#define  RTC_CR_BCK                          ((uint32_t)0x00040000)
#define  RTC_CR_SUB1H                        ((uint32_t)0x00020000)
#define  RTC_CR_ADD1H                        ((uint32_t)0x00010000)
#define  RTC_CR_WUTIE                        ((uint32_t)0x00004000)
#define  RTC_CR_ALRAIE                       ((uint32_t)0x00001000)
#define  RTC_CR_WUTE                         ((uint32_t)0x00000400)
#define  RTC_CR_ALRAE                        ((uint32_t)0x00000100)
#define  RTC_CR_FMT                          ((uint32_t)0x00000040)
#define  RTC_CR_BYPSHAD                      ((uint32_t)0x00000020)
#define  RTC_CR_WUCKSEL                      ((uint32_t)0x00000007)
#define  RTC_CR_WUCKSEL_0                    ((uint32_t)0x00000001)
#define  RTC_CR_WUCKSEL_1                    ((uint32_t)0x00000002)
#define  RTC_CR_WUCKSEL_2                    ((uint32_t)0x00000004)

/********************  Bits definition for RTC_ISR register  ******************/
#define  RTC_ISR_RECALPF                     ((uint32_t)0x00010000)
#define  RTC_ISR_WUTF                        ((uint32_t)0x00000400)
#define  RTC_ISR_ALRAF                       ((uint32_t)0x00000100)
#define  RTC_ISR_INIT                        ((uint32_t)0x00000080)
#define  RTC_ISR_INITF                       ((uint32_t)0x00000040)
#define  RTC_ISR_RSF                         ((uint32_t)0x00000020)
#define  RTC_ISR_INITS                       ((uint32_t)0x00000010)
#define  RTC_ISR_SHPF                        ((uint32_t)0x00000008)
#define  RTC_ISR_WUTWF                       ((uint32_t)0x00000004)
#define  RTC_ISR_ALRAWF                      ((uint32_t)0x00000001)

/********************  Bits definition for RTC_PRER register  *****************/
#define  RTC_PRER_PREDIV_A                   ((uint32_t)0x007F0000)
#define  RTC_PRER_PREDIV_S                   ((uint32_t)0x00007FFF)

/********************  Bits definition for RTC_WUTR register  *****************/
#define  RTC_WUTR_WUT                        ((uint32_t)0x0000FFFF)

/********************  Bits definition for RTC_CALIBR register  ***************/
#define  RTC_CALIBR_DCS                      ((uint32_t)0x00000080)
#define  RTC_CALIBR_DC                       ((uint32_t)0x0000001F)

/********************  Bits definition for RTC_ALRMAR register  ***************/
#define  RTC_ALRMAR_MSK4                     ((uint32_t)0x80000000)
#define  RTC_ALRMAR_WDSEL                    ((uint32_t)0x40000000)
#define  RTC_ALRMAR_DT                       ((uint32_t)0x30000000)
#define  RTC_ALRMAR_DT_0                     ((uint32_t)0x10000000)
#define  RTC_ALRMAR_DT_1                     ((uint32_t)0x20000000)
#define  RTC_ALRMAR_DU                       ((uint32_t)0x0F000000)
#define  RTC_ALRMAR_DU_0                     ((uint32_t)0x01000000)
#define  RTC_ALRMAR_DU_1                     ((uint32_t)0x02000000)
#define  RTC_ALRMAR_DU_2                     ((uint32_t)0x04000000)
#define  RTC_ALRMAR_DU_3                     ((uint32_t)0x08000000)
#define  RTC_ALRMAR_MSK3                     ((uint32_t)0x00800000)
#define  RTC_ALRMAR_PM                       ((uint32_t)0x00400000)
#define  RTC_ALRMAR_HT                       ((uint32_t)0x00300000)
#define  RTC_ALRMAR_HT_0                     ((uint32_t)0x00100000)
#define  RTC_ALRMAR_HT_1                     ((uint32_t)0x00200000)
#define  RTC_ALRMAR_HU                       ((uint32_t)0x000F0000)
#define  RTC_ALRMAR_HU_0                     ((uint32_t)0x00010000)
#define  RTC_ALRMAR_HU_1                     ((uint32_t)0x00020000)
#define  RTC_ALRMAR_HU_2                     ((uint32_t)0x00040000)
#define  RTC_ALRMAR_HU_3                     ((uint32_t)0x00080000)
#define  RTC_ALRMAR_MSK2                     ((uint32_t)0x00008000)
#define  RTC_ALRMAR_MNT                      ((uint32_t)0x00007000)
#define  RTC_ALRMAR_MNT_0                    ((uint32_t)0x00001000)
#define  RTC_ALRMAR_MNT_1                    ((uint32_t)0x00002000)
#define  RTC_ALRMAR_MNT_2                    ((uint32_t)0x00004000)
#define  RTC_ALRMAR_MNU                      ((uint32_t)0x00000F00)
#define  RTC_ALRMAR_MNU_0                    ((uint32_t)0x00000100)
#define  RTC_ALRMAR_MNU_1                    ((uint32_t)0x00000200)
#define  RTC_ALRMAR_MNU_2                    ((uint32_t)0x00000400)
#define  RTC_ALRMAR_MNU_3                    ((uint32_t)0x00000800)
#define  RTC_ALRMAR_MSK1                     ((uint32_t)0x00000080)
#define  RTC_ALRMAR_ST                       ((uint32_t)0x00000070)
#define  RTC_ALRMAR_ST_0                     ((uint32_t)0x00000010)
#define  RTC_ALRMAR_ST_1                     ((uint32_t)0x00000020)
#define  RTC_ALRMAR_ST_2                     ((uint32_t)0x00000040)
#define  RTC_ALRMAR_SU                       ((uint32_t)0x0000000F)
#define  RTC_ALRMAR_SU_0                     ((uint32_t)0x00000001)
#define  RTC_ALRMAR_SU_1                     ((uint32_t)0x00000002)
#define  RTC_ALRMAR_SU_2                     ((uint32_t)0x00000004)
#define  RTC_ALRMAR_SU_3                     ((uint32_t)0x00000008)

/********************  Bits definition for RTC_ALRMBR register  ***************/
#define  RTC_ALRMBR_MSK4                     ((uint32_t)0x80000000)
#define  RTC_ALRMBR_WDSEL                    ((uint32_t)0x40000000)
#define  RTC_ALRMBR_DT                       ((uint32_t)0x30000000)
#define  RTC_ALRMBR_DT_0                     ((uint32_t)0x10000000)
#define  RTC_ALRMBR_DT_1                     ((uint32_t)0x20000000)
#define  RTC_ALRMBR_DU                       ((uint32_t)0x0F000000)
#define  RTC_ALRMBR_DU_0                     ((uint32_t)0x01000000)
#define  RTC_ALRMBR_DU_1                     ((uint32_t)0x02000000)
#define  RTC_ALRMBR_DU_2                     ((uint32_t)0x04000000)
#define  RTC_ALRMBR_DU_3                     ((uint32_t)0x08000000)
#define  RTC_ALRMBR_MSK3                     ((uint32_t)0x00800000)
#define  RTC_ALRMBR_PM                       ((uint32_t)0x00400000)
#define  RTC_ALRMBR_HT                       ((uint32_t)0x00300000)
#define  RTC_ALRMBR_HT_0                     ((uint32_t)0x00100000)
#define  RTC_ALRMBR_HT_1                     ((uint32_t)0x00200000)
#define  RTC_ALRMBR_HU                       ((uint32_t)0x000F0000)
#define  RTC_ALRMBR_HU_0                     ((uint32_t)0x00010000)
#define  RTC_ALRMBR_HU_1                     ((uint32_t)0x00020000)
#define  RTC_ALRMBR_HU_2                     ((uint32_t)0x00040000)
#define  RTC_ALRMBR_HU_3                     ((uint32_t)0x00080000)
#define  RTC_ALRMBR_MSK2                     ((uint32_t)0x00008000)
#define  RTC_ALRMBR_MNT                      ((uint32_t)0x00007000)
#define  RTC_ALRMBR_MNT_0                    ((uint32_t)0x00001000)
#define  RTC_ALRMBR_MNT_1                    ((uint32_t)0x00002000)
#define  RTC_ALRMBR_MNT_2                    ((uint32_t)0x00004000)
#define  RTC_ALRMBR_MNU                      ((uint32_t)0x00000F00)
#define  RTC_ALRMBR_MNU_0                    ((uint32_t)0x00000100)
#define  RTC_ALRMBR_MNU_1                    ((uint32_t)0x00000200)
#define  RTC_ALRMBR_MNU_2                    ((uint32_t)0x00000400)
#define  RTC_ALRMBR_MNU_3                    ((uint32_t)0x00000800)
#define  RTC_ALRMBR_MSK1                     ((uint32_t)0x00000080)
#define  RTC_ALRMBR_ST                       ((uint32_t)0x00000070)
#define  RTC_ALRMBR_ST_0                     ((uint32_t)0x00000010)
#define  RTC_ALRMBR_ST_1                     ((uint32_t)0x00000020)
#define  RTC_ALRMBR_ST_2                     ((uint32_t)0x00000040)
#define  RTC_ALRMBR_SU                       ((uint32_t)0x0000000F)
#define  RTC_ALRMBR_SU_0                     ((uint32_t)0x00000001)
#define  RTC_ALRMBR_SU_1                     ((uint32_t)0x00000002)
#define  RTC_ALRMBR_SU_2                     ((uint32_t)0x00000004)
#define  RTC_ALRMBR_SU_3                     ((uint32_t)0x00000008)

/********************  Bits definition for RTC_WPR register  ******************/
#define  RTC_WPR_KEY                         ((uint32_t)0x000000FF)

/********************  Bits definition for RTC_SSR register  ******************/
#define  RTC_SSR_SS                          ((uint32_t)0x0000FFFF)

/********************  Bits definition for RTC_SHIFTR register  ***************/
#define  RTC_SHIFTR_SUBFS                    ((uint32_t)0x00007FFF)
#define  RTC_SHIFTR_ADD1S                    ((uint32_t)0x80000000)

/********************  Bits definition for RTC_CAL register  *****************/
#define  RTC_CALR_CALP                       ((uint32_t)0x00008000)
#define  RTC_CALR_CALW8                      ((uint32_t)0x00004000)
#define  RTC_CALR_CALW16                     ((uint32_t)0x00002000)
#define  RTC_CALR_CALM                       ((uint32_t)0x000001FF)
#define  RTC_CALR_CALM_0                     ((uint32_t)0x00000001)
#define  RTC_CALR_CALM_1                     ((uint32_t)0x00000002)
#define  RTC_CALR_CALM_2                     ((uint32_t)0x00000004)
#define  RTC_CALR_CALM_3                     ((uint32_t)0x00000008)
#define  RTC_CALR_CALM_4                     ((uint32_t)0x00000010)
#define  RTC_CALR_CALM_5                     ((uint32_t)0x00000020)
#define  RTC_CALR_CALM_6                     ((uint32_t)0x00000040)
#define  RTC_CALR_CALM_7                     ((uint32_t)0x00000080)
#define  RTC_CALR_CALM_8                     ((uint32_t)0x00000100)

/********************  Bits definition for RTC_ALRMASSR register  *************/
#define  RTC_ALRMASSR_MASKSS                 ((uint32_t)0x0F000000)
#define  RTC_ALRMASSR_MASKSS_0               ((uint32_t)0x01000000)
#define  RTC_ALRMASSR_MASKSS_1               ((uint32_t)0x02000000)
#define  RTC_ALRMASSR_MASKSS_2               ((uint32_t)0x04000000)
#define  RTC_ALRMASSR_MASKSS_3               ((uint32_t)0x08000000)
#define  RTC_ALRMASSR_SS                     ((uint32_t)0x00007FFF)

/********************  Bits definition for RTC_BKP0R register  ****************/
#define  RTC_BKP0R                           ((uint32_t)0xFFFFFFFF)


/******************************************************************************/
/*                                                                            */
/*                        Serial Peripheral Interface (SPI)                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SPI_CR1 register  ********************/
#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< CRC Length */
#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */

/*******************  Bit definition for SPI_CR2 register  ********************/
#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */

/********************  Bit definition for SPI_SR register  ********************/
#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */

/********************  Bit definition for SPI_DR register  ********************/
#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */

/*******************  Bit definition for SPI_CRCPR register  ******************/
#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */

/******************  Bit definition for SPI_RXCRCR register  ******************/
#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */

/******************  Bit definition for SPI_TXCRCR register  ******************/
#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */




/******************************************************************************/
/*                                                                            */
/*                       System Configuration (SYSCFG)                        */
/*                                                                            */
/******************************************************************************/
/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
#define  SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define  SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define  SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */

/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
#define  SYSCFG_CFGR2_LOCKUP_LOCK            ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */

/*****************  Bit definition for SYSCFG_PORTCR register  ***************/
#define  SYSCFG_PORTCR_SPINSSSEL             ((uint32_t)0x0000000F) /*!< NSS SEL configuration */

/**
  * @brief  PCA configuration
  */
#define  SYSCFG_PCACR_CAP0_SEL               ((uint32_t)0x00000003) 
#define  SYSCFG_PCACR_CAP1_SEL               ((uint32_t)0x0000000C) 
#define  SYSCFG_PCACR_CAP2_SEL               ((uint32_t)0x00000030) 
#define  SYSCFG_PCACR_CAP3_SEL               ((uint32_t)0x000000C0) 
#define  SYSCFG_PCACR_CAP4_SEL               ((uint32_t)0x00000300) 

/**
  * @brief  TIM1 configuration
  */
#define  SYSCFG_TIM1CR_CH1IN_SEL             ((uint32_t)0x00000007) 
#define  SYSCFG_TIM1CR_CH2IN_SEL             ((uint32_t)0x00000070) 
#define  SYSCFG_TIM1CR_CH3IN_SEL             ((uint32_t)0x00000700) 
#define  SYSCFG_TIM1CR_CH4IN_SEL             ((uint32_t)0x00007000) 
#define  SYSCFG_TIM1CR_ETR_SEL               ((uint32_t)0x000F0000) 

/**
  * @brief  TIM2 configuration
  */
#define  SYSCFG_TIM2CR_CH1IN_SEL             ((uint32_t)0x00000007) 
#define  SYSCFG_TIM2CR_CH2IN_SEL             ((uint32_t)0x00000070) 
#define  SYSCFG_TIM2CR_CH3IN_SEL             ((uint32_t)0x00000700) 
#define  SYSCFG_TIM2CR_CH4IN_SEL             ((uint32_t)0x00007000) 
#define  SYSCFG_TIM2CR_ETR_SEL               ((uint32_t)0x000F0000) 


/******************************************************************************/
/*                                                                            */
/*                               Timers (TIM)                                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TIM_CR1 register  ********************/
#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
#define  TIM_CR1_TOG_EN                      ((uint16_t)0x0010)            /*!<Tog enable */

#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */

#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */

#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */

/*******************  Bit definition for TIM_CR2 register  ********************/
#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */

#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */

#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */

/*******************  Bit definition for TIM_SMCR register  *******************/
#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */

#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */

#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */

#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */

#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */

#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */

/*******************  Bit definition for TIM_DIER register  *******************/
#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */

/********************  Bit definition for TIM_SR register  ********************/
#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */

/*******************  Bit definition for TIM_EGR register  ********************/
#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */

/******************  Bit definition for TIM_CCMR1 register  *******************/
#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */

#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */

#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */

#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */

#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */

#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */

#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */

#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */

/*----------------------------------------------------------------------------*/

#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */

#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */

#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */

#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */

/******************  Bit definition for TIM_CCMR2 register  *******************/
#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */

#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */

#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */

#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */

#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */

#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */

#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */

#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */

/*----------------------------------------------------------------------------*/

#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */

#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */

#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */

#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */

/*******************  Bit definition for TIM_CCER register  *******************/
#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */

/*******************  Bit definition for TIM_CNT register  ********************/
#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */

/*******************  Bit definition for TIM_PSC register  ********************/
#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */

/*******************  Bit definition for TIM_ARR register  ********************/
#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */

/*******************  Bit definition for TIM_RCR register  ********************/
#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */

/*******************  Bit definition for TIM_CCR1 register  *******************/
#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */

/*******************  Bit definition for TIM_CCR2 register  *******************/
#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */

/*******************  Bit definition for TIM_CCR3 register  *******************/
#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */

/*******************  Bit definition for TIM_CCR4 register  *******************/
#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */

/*******************  Bit definition for TIM_BDTR register  *******************/
#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */

#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */

#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */

/*******************  Bit definition for TIM_DCR register  ********************/
#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */

#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */

/*******************  Bit definition for TIM_DMAR register  *******************/
#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */


/******************************************************************************/
/*                                                                            */
/*         Universal Synchronous Asynchronous Receiver Transmitter            */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for USART_SR register  *******************/
#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */

/*******************  Bit definition for USART_DR register  *******************/
#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */

/******************  Bit definition for USART_BRR register  *******************/
#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */

/******************  Bit definition for USART_CR1 register  *******************/
#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */

/******************  Bit definition for USART_CR2 register  *******************/
#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */

#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */

#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */

/******************  Bit definition for USART_CR3 register  *******************/
#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */

/******************  Bit definition for USART_GTPR register  ******************/
#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */

#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */


/******************************************************************************/
/*                                                                            */
/*                         Window WATCHDOG (WWDG)                             */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for WWDG_CR register  ********************/
#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */

#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */

/*******************  Bit definition for WWDG_CFR register  *******************/
#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */

#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */

#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */

/*******************  Bit definition for WWDG_SR register  ********************/
#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */




/******************************************************************************/
/*  For a painless codes migration between the tc32l010 device product       */
/*  lines, the aliases defined below are put in place to overcome the         */
/*  differences in the interrupt handlers and IRQn definitions.               */
/*  No need to update developed interrupt code when moving across             */
/*  product lines within the same tc32l010 Family                              */
/******************************************************************************/



/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __XS32L010_H */



/************************ (C) COPYRIGHT CHIPAT *****END OF FILE****/
